-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L84 is p1_3~2 at LC33
A1L84_or_out = p1_3;
A1L84 = A1L84_or_out;


--A1L05 is p1_4~2 at LC19
A1L05_or_out = p1_4;
A1L05 = A1L05_or_out;


--A1L75 is sel_out0~6 at LC4
A1L75_p1_out = !sel_addr1 & !cpld_sel & !sel_addr0;
A1L75_or_out = A1L75_p1_out;
A1L75 = A1L75_or_out;


--A1L95 is sel_out1~11 at LC3
A1L95_p1_out = !sel_addr1 & !cpld_sel & sel_addr0;
A1L95_or_out = A1L95_p1_out;
A1L95 = !(A1L95_or_out);


--A1L16 is sel_out2~16 at LC64
A1L16_p1_out = sel_addr1 & !cpld_sel & !sel_addr0 & !rd;
A1L16_or_out = A1L16_p1_out;
A1L16 = !(A1L16_or_out);


--A1L36 is sel_out3~13 at LC1
A1L36_p1_out = sel_addr1 & !cpld_sel & sel_addr0;
A1L36_or_out = A1L36_p1_out;
A1L36 = !(A1L36_or_out);


--B1_dffs[0] is lpm_counter:addr_count_rtl_2|dffs[0] at LC58
B1_dffs[0]_or_out = cpld_sel;
B1_dffs[0]_reg_input = B1_dffs[0]_or_out;
B1_dffs[0] = TFFE(B1_dffs[0]_reg_input, p1_3, p1_5, , );


--temp[6] is temp[6] at LC45
temp[6]_p1_out = din[6] & cpld_sel;
temp[6]_p2_out = !cpld_sel & temp[6];
temp[6]_or_out = temp[6]_p1_out # temp[6]_p2_out;
temp[6]_reg_input = temp[6]_or_out;
temp[6] = DFFE(temp[6]_reg_input, wr, GLOBAL(p1_6), , );


--temp[5] is temp[5] at LC39
temp[5]_p1_out = din[5] & cpld_sel;
temp[5]_p2_out = !cpld_sel & temp[5];
temp[5]_or_out = temp[5]_p1_out # temp[5]_p2_out;
temp[5]_reg_input = temp[5]_or_out;
temp[5] = DFFE(temp[5]_reg_input, wr, GLOBAL(p1_6), , );


--temp[4] is temp[4] at LC38
temp[4]_p1_out = din[4] & cpld_sel;
temp[4]_p2_out = !cpld_sel & temp[4];
temp[4]_or_out = temp[4]_p1_out # temp[4]_p2_out;
temp[4]_reg_input = temp[4]_or_out;
temp[4] = DFFE(temp[4]_reg_input, wr, GLOBAL(p1_6), , );


--temp[3] is temp[3] at LC46
temp[3]_p1_out = din[3] & cpld_sel;
temp[3]_p2_out = !cpld_sel & temp[3];
temp[3]_or_out = temp[3]_p1_out # temp[3]_p2_out;
temp[3]_reg_input = temp[3]_or_out;
temp[3] = DFFE(temp[3]_reg_input, wr, GLOBAL(p1_6), , );


--temp[2] is temp[2] at LC22
temp[2]_p1_out = din[2] & cpld_sel;
temp[2]_p2_out = !cpld_sel & temp[2];
temp[2]_or_out = temp[2]_p1_out # temp[2]_p2_out;
temp[2]_reg_input = temp[2]_or_out;
temp[2] = DFFE(temp[2]_reg_input, wr, GLOBAL(p1_6), , );


--temp[1] is temp[1] at LC23
temp[1]_p1_out = din[1] & cpld_sel;
temp[1]_p2_out = !cpld_sel & temp[1];
temp[1]_or_out = temp[1]_p1_out # temp[1]_p2_out;
temp[1]_reg_input = temp[1]_or_out;
temp[1] = DFFE(temp[1]_reg_input, wr, GLOBAL(p1_6), , );


--temp[0] is temp[0] at LC30
temp[0]_p1_out = din[0] & cpld_sel;
temp[0]_p2_out = !cpld_sel & temp[0];
temp[0]_or_out = temp[0]_p1_out # temp[0]_p2_out;
temp[0]_reg_input = temp[0]_or_out;
temp[0] = DFFE(temp[0]_reg_input, wr, GLOBAL(p1_6), , );


--flag_counter is flag_counter at LC2
flag_counter_p1_out = !flag_counter & !cpld_sel;
flag_counter_or_out = flag_counter_p1_out;
flag_counter_reg_input = !(flag_counter_or_out);
flag_counter = DFFE(flag_counter_reg_input, wr, GLOBAL(p1_6), , );


--temp[7] is temp[7] at LC32
temp[7]_p1_out = din[7] & cpld_sel;
temp[7]_p2_out = !cpld_sel & temp[7];
temp[7]_or_out = temp[7]_p1_out # temp[7]_p2_out;
temp[7]_reg_input = temp[7]_or_out;
temp[7] = DFFE(temp[7]_reg_input, wr, GLOBAL(p1_6), , );


--flag_low is flag_low at LC57
flag_low_p0_out = flag_counter & wr & flag_data & !H2_6 & !H2_7 & !H2_8;
flag_low_p1_out = !H2_5 & flag_counter & wr & flag_data;
flag_low_p3_out = flag_counter & wr & flag_low & !H2_6 & !H2_7 & !H2_8;
flag_low_or_out = A1L63 # flag_low_p0_out # flag_low_p1_out # flag_low_p3_out;
flag_low_reg_input = flag_low_or_out;
flag_low_p2_out = !flag_low & !cpld_sel & !p1_6;
flag_low_p4_out = !p1_6 & A1L53;
flag_low = TFFE(flag_low_reg_input, GLOBAL(clk), !flag_low_p2_out, !flag_low_p4_out, );


--A1L2Q is addr_out0~reg0 at LC40
A1L2Q_p1_out = B1_dffs[0] & cpld_sel & p1_5 & !A1L2Q;
A1L2Q_p2_out = !B1_dffs[0] & cpld_sel & p1_5 & A1L2Q;
A1L2Q_or_out = A1L2Q_p1_out # A1L2Q_p2_out;
A1L2Q_reg_input = A1L2Q_or_out;
A1L2Q = TFFE(A1L2Q_reg_input, p1_3, , , );


--B1_dffs[1] is lpm_counter:addr_count_rtl_2|dffs[1] at LC49
B1_dffs[1]_p1_out = cpld_sel & B1_dffs[0];
B1_dffs[1]_or_out = B1_dffs[1]_p1_out;
B1_dffs[1]_reg_input = B1_dffs[1]_or_out;
B1_dffs[1] = TFFE(B1_dffs[1]_reg_input, p1_3, p1_5, , );


--flag_data is flag_data at LC62
flag_data_p0_out = !flag_low & flag_counter & wr & flag_data & !H2_5;
flag_data_p1_out = !H2_6 & !H2_7 & !H2_8 & flag_low & flag_counter & wr & !flag_data;
flag_data_p3_out = !H2_6 & !H2_7 & !H2_8 & !flag_low & flag_counter & wr & flag_data;
flag_data_or_out = A1L73 # flag_data_p0_out # flag_data_p1_out # flag_data_p3_out;
flag_data_reg_input = flag_data_or_out;
flag_data_p2_out = !p1_6 & A1L13;
flag_data_p4_out = flag_data & !p1_6 & !cpld_sel;
flag_data = TFFE(flag_data_reg_input, GLOBAL(clk), !flag_data_p2_out, !flag_data_p4_out, );


--A1L4Q is addr_out1~reg0 at LC37
A1L4Q_p1_out = B1_dffs[1] & cpld_sel & p1_5 & !A1L4Q;
A1L4Q_p2_out = !B1_dffs[1] & cpld_sel & p1_5 & A1L4Q;
A1L4Q_or_out = A1L4Q_p1_out # A1L4Q_p2_out;
A1L4Q_reg_input = A1L4Q_or_out;
A1L4Q = TFFE(A1L4Q_reg_input, p1_3, , , );


--B1_dffs[2] is lpm_counter:addr_count_rtl_2|dffs[2] at LC50
B1_dffs[2]_p1_out = B1_dffs[1] & cpld_sel & B1_dffs[0];
B1_dffs[2]_or_out = B1_dffs[2]_p1_out;
B1_dffs[2]_reg_input = B1_dffs[2]_or_out;
B1_dffs[2] = TFFE(B1_dffs[2]_reg_input, p1_3, p1_5, , );


--A1L6Q is addr_out2~reg0 at LC36
A1L6Q_p1_out = B1_dffs[2] & cpld_sel & p1_5 & !A1L6Q;
A1L6Q_p2_out = !B1_dffs[2] & cpld_sel & p1_5 & A1L6Q;
A1L6Q_or_out = A1L6Q_p1_out # A1L6Q_p2_out;
A1L6Q_reg_input = A1L6Q_or_out;
A1L6Q = TFFE(A1L6Q_reg_input, p1_3, , , );


--B1_dffs[3] is lpm_counter:addr_count_rtl_2|dffs[3] at LC34
B1_dffs[3]_p1_out = B1_dffs[2] & B1_dffs[1] & cpld_sel & B1_dffs[0];
B1_dffs[3]_or_out = B1_dffs[3]_p1_out;
B1_dffs[3]_reg_input = B1_dffs[3]_or_out;
B1_dffs[3] = TFFE(B1_dffs[3]_reg_input, p1_3, p1_5, , );


--H2_8 is lpm_counter:data_count_rtl_1|p8count:p8c[0]|8 at LC10
H2_8_p0_out = flag_counter & wr & !flag_low & flag_data & !H2_6 & !H2_7 & !H2_8;
H2_8_p1_out = !H2_5 & flag_counter & wr & !flag_low & flag_data;
H2_8_p3_out = flag_counter & wr & flag_low & !flag_init & !H2_6 & !H2_7 & !H2_8;
H2_8_or_out = H2L5 # H2_8_p0_out # H2_8_p1_out # H2_8_p3_out;
H2_8_reg_input = H2_8_or_out;
H2_8_p2_out = H2L9 & !p1_6;
H2_8_p4_out = H2_8 & !p1_6 & !cpld_sel;
H2_8 = TFFE(H2_8_reg_input, GLOBAL(clk), !H2_8_p2_out, !H2_8_p4_out, );


--H2L9 is lpm_counter:data_count_rtl_1|p8count:p8c[0]|142~21 at SEXP1
H2L9 = EXP(!cpld_sel & H2_8);


--A1L8Q is addr_out3~reg0 at LC35
A1L8Q_p1_out = B1_dffs[3] & cpld_sel & p1_5 & !A1L8Q;
A1L8Q_p2_out = !B1_dffs[3] & cpld_sel & p1_5 & A1L8Q;
A1L8Q_or_out = A1L8Q_p1_out # A1L8Q_p2_out;
A1L8Q_reg_input = A1L8Q_or_out;
A1L8Q = TFFE(A1L8Q_reg_input, p1_3, , , );


--H2_7 is lpm_counter:data_count_rtl_1|p8count:p8c[0]|7 at LC8
H2_7_p1_out = !flag_init & H2_8 & !H2_5 & flag_counter & wr & flag_low;
H2_7_p3_out = H2_8 & !H2_5 & flag_counter & wr & !flag_low & flag_data;
H2_7_or_out = H2_7_p1_out # H2_7_p3_out;
H2_7_reg_input = H2_7_or_out;
H2_7_p2_out = H2L8 & !p1_6;
H2_7_p4_out = !p1_6 & !cpld_sel & H2_7;
H2_7 = TFFE(H2_7_reg_input, GLOBAL(clk), !H2_7_p2_out, !H2_7_p4_out, );


--H2L8 is lpm_counter:data_count_rtl_1|p8count:p8c[0]|138~21 at SEXP2
H2L8 = EXP(!cpld_sel & H2_7);


--H2_6 is lpm_counter:data_count_rtl_1|p8count:p8c[0]|6 at LC16
H2_6_p1_out = !flag_init & H2_7 & H2_8 & !H2_5 & flag_counter & wr & flag_low;
H2_6_p3_out = H2_7 & H2_8 & !H2_5 & flag_counter & wr & !flag_low & flag_data;
H2_6_or_out = H2_6_p1_out # H2_6_p3_out;
H2_6_reg_input = H2_6_or_out;
H2_6_p2_out = H2L7 & !p1_6;
H2_6_p4_out = !p1_6 & !cpld_sel & H2_6;
H2_6 = TFFE(H2_6_reg_input, GLOBAL(clk), !H2_6_p2_out, !H2_6_p4_out, );


--H2L7 is lpm_counter:data_count_rtl_1|p8count:p8c[0]|125~21 at SEXP3
H2L7 = EXP(!cpld_sel & H2_6);


--H2_5 is lpm_counter:data_count_rtl_1|p8count:p8c[0]|5 at LC5
H2_5_p1_out = !flag_init & H2_6 & H2_7 & H2_8 & !H2_5 & flag_counter & wr & flag_low;
H2_5_p3_out = H2_6 & H2_7 & H2_8 & !H2_5 & flag_counter & wr & !flag_low & flag_data;
H2_5_or_out = H2_5_p1_out # H2_5_p3_out;
H2_5_reg_input = H2_5_or_out;
H2_5_p2_out = H2L6 & !p1_6;
H2_5_p4_out = H2_5 & !p1_6 & !cpld_sel;
H2_5 = TFFE(H2_5_reg_input, GLOBAL(clk), !H2_5_p2_out, !H2_5_p4_out, );


--H2L6 is lpm_counter:data_count_rtl_1|p8count:p8c[0]|124~21 at SEXP4
H2L6 = EXP(!cpld_sel & H2_5);


--A1L41Q is clk_out~reg0 at LC26
A1L41Q_p0_out = flag_low & !H2_6 & !H2_7 & !H2_8 & flag_counter & wr & A1L41Q;
A1L41Q_p1_out = flag_data & !flag_low & !H2_6 & !H2_7 & !H2_8 & flag_counter & wr & !A1L41Q;
A1L41Q_p3_out = flag_low & flag_counter & wr & A1L41Q & !H2_5;
A1L41Q_or_out = A1L21 # A1L41Q_p0_out # A1L41Q_p1_out # A1L41Q_p3_out;
A1L41Q_reg_input = A1L41Q_or_out;
A1L41Q_p2_out = !p1_6 & A1L11;
A1L41Q_p4_out = A1L41Q & !p1_6 & !cpld_sel;
A1L41Q = TFFE(A1L41Q_reg_input, GLOBAL(clk), !A1L41Q_p2_out, !A1L41Q_p4_out, );


--flag_init is flag_init at LC15
flag_init_p1_out = !H2_5 & flag_counter & wr & flag_low & !flag_init;
flag_init_p3_out = flag_counter & wr & flag_low & !flag_init & !H2_6 & !H2_7 & !H2_8;
flag_init_or_out = flag_init_p1_out # flag_init_p3_out;
flag_init_reg_input = flag_init_or_out;
flag_init_p2_out = !p1_6 & A1L33;
flag_init_p4_out = flag_init & !p1_6 & !cpld_sel;
flag_init = TFFE(flag_init_reg_input, GLOBAL(clk), !flag_init_p2_out, !flag_init_p4_out, );


--B2_dffs[0] is lpm_counter:counter_rtl_0|dffs[0] at LC7
B2_dffs[0]_p0_out = flag_counter & wr & !flag_low & flag_data & !H2_6 & !H2_7 & !H2_8;
B2_dffs[0]_p1_out = !H2_5 & flag_counter & wr & !flag_low & flag_data;
B2_dffs[0]_p3_out = flag_counter & wr & flag_low & !flag_init & !H2_6 & !H2_7 & !H2_8;
B2_dffs[0]_or_out = B2L1 # B2_dffs[0]_p0_out # B2_dffs[0]_p1_out # B2_dffs[0]_p3_out;
B2_dffs[0]_reg_input = B2_dffs[0]_or_out;
B2_dffs[0]_p2_out = !p1_6 & A1L51;
B2_dffs[0]_p4_out = !p1_6 & B2_dffs[0] & !cpld_sel;
B2_dffs[0] = TFFE(B2_dffs[0]_reg_input, GLOBAL(clk), !B2_dffs[0]_p2_out, !B2_dffs[0]_p4_out, );


--B2_dffs[1] is lpm_counter:counter_rtl_0|dffs[1] at LC12
B2_dffs[1]_p0_out = !B2_dffs[0] & flag_counter & wr & !flag_low & flag_data & !H2_6 & !H2_7 & !H2_8;
B2_dffs[1]_p1_out = !H2_5 & !B2_dffs[0] & flag_counter & wr & !flag_low & flag_data;
B2_dffs[1]_p3_out = !B2_dffs[0] & flag_counter & wr & flag_low & !flag_init & !H2_6 & !H2_7 & !H2_8;
B2_dffs[1]_or_out = B2L2 # B2_dffs[1]_p0_out # B2_dffs[1]_p1_out # B2_dffs[1]_p3_out;
B2_dffs[1]_reg_input = B2_dffs[1]_or_out;
B2_dffs[1]_p2_out = !p1_6 & A1L61;
B2_dffs[1]_p4_out = !p1_6 & B2_dffs[1] & !cpld_sel;
B2_dffs[1] = TFFE(B2_dffs[1]_reg_input, GLOBAL(clk), !B2_dffs[1]_p2_out, !B2_dffs[1]_p4_out, );


--B2_dffs[2] is lpm_counter:counter_rtl_0|dffs[2] at LC14
B2_dffs[2]_p0_out = !B2_dffs[1] & !B2_dffs[0] & flag_counter & wr & !flag_low & flag_data & !H2_6 & !H2_7 & !H2_8;
B2_dffs[2]_p1_out = !H2_5 & !B2_dffs[1] & !B2_dffs[0] & flag_counter & wr & !flag_low & flag_data;
B2_dffs[2]_p3_out = !B2_dffs[1] & !B2_dffs[0] & flag_counter & wr & flag_low & !flag_init & !H2_6 & !H2_7 & !H2_8;
B2_dffs[2]_or_out = B2L3 # B2_dffs[2]_p0_out # B2_dffs[2]_p1_out # B2_dffs[2]_p3_out;
B2_dffs[2]_reg_input = B2_dffs[2]_or_out;
B2_dffs[2]_p2_out = !p1_6 & A1L71;
B2_dffs[2]_p4_out = !p1_6 & B2_dffs[2] & !cpld_sel;
B2_dffs[2] = TFFE(B2_dffs[2]_reg_input, GLOBAL(clk), !B2_dffs[2]_p2_out, !B2_dffs[2]_p4_out, );


--A1L34 is Mux~600 at SEXP23
A1L34 = EXP(!temp[6] & B2_dffs[2] & B2_dffs[0] & B2_dffs[1]);


--A1L44 is Mux~601 at SEXP25
A1L44 = EXP(!temp[3] & B2_dffs[2] & !B2_dffs[0] & !B2_dffs[1]);


--A1L54 is Mux~602 at SEXP28
A1L54 = EXP(B2_dffs[2] & !B2_dffs[0] & B2_dffs[1] & !temp[5]);


--A1L47Q is serial_or~reg0 at LC20
A1L47Q_p1_out = A1L34 & A1L44 & A1L54 & A1L83 & A1L93 & A1L04 & A1L14 & A1L24;
A1L47Q_or_out = A1L47Q_p1_out;
A1L47Q_reg_input = !(A1L47Q_or_out);
A1L47Q_p2_out = !A1L47Q & !cpld_sel & !p1_6;
A1L47Q_p4_out = !p1_6 & A1L86;
A1L47Q_p3_out = A1L96 & A1L07 & A1L17 & A1L27 & d_sel & flag_counter & wr & A1L37;