?? tiaoping.pin
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (3.3V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- NON_MIGRATABLE: This pin cannot be migrated.
---------------------------------------------------------------------------------
Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version
CHIP "tiaoping" ASSIGNED TO AN: EPM7064AETC44-10
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
TDI : 1 : input : LVTTL : : : N
p1_4 : 2 : input : LVTTL : : : Y
sel_out0 : 3 : output : LVTTL : : : Y
GND : 4 : gnd : : : :
sel_out1 : 5 : output : LVTTL : : : Y
sel_out3 : 6 : output : LVTTL : : : Y
TMS : 7 : input : LVTTL : : : N
p1_3 : 8 : input : LVTTL : : : Y
VCCIO : 9 : power : : 3.3V : :
wr : 10 : input : LVTTL : : : Y
rd : 11 : input : LVTTL : : : Y
serial_og : 12 : output : LVTTL : : : Y
serial_or : 13 : output : LVTTL : : : Y
oe_out : 14 : output : LVTTL : : : Y
clk_out : 15 : output : LVTTL : : : Y
GND : 16 : gnd : : : :
VCCINT : 17 : power : : 3.3V : :
xlat : 18 : output : LVTTL : : : Y
addr_out3 : 19 : output : LVTTL : : : Y
addr_out2 : 20 : output : LVTTL : : : Y
addr_out1 : 21 : output : LVTTL : : : Y
addr_out0 : 22 : output : LVTTL : : : Y
din[7] : 23 : input : LVTTL : : : Y
GND : 24 : gnd : : : :
din[6] : 25 : input : LVTTL : : : Y
TCK : 26 : input : LVTTL : : : N
din[5] : 27 : input : LVTTL : : : Y
din[4] : 28 : input : LVTTL : : : Y
VCCIO : 29 : power : : 3.3V : :
din[3] : 30 : input : LVTTL : : : Y
din[2] : 31 : input : LVTTL : : : Y
TDO : 32 : output : LVTTL : : : N
din[1] : 33 : input : LVTTL : : : Y
din[0] : 34 : input : LVTTL : : : Y
sel_out2 : 35 : output : LVTTL : : : Y
GND : 36 : gnd : : : :
clk : 37 : input : LVTTL : : : Y
p1_5 : 38 : input : LVTTL : : : Y
p1_6 : 39 : input : LVTTL : : : Y
d_sel : 40 : input : LVTTL : : : Y
VCCINT : 41 : power : : 3.3V : :
cpld_sel : 42 : input : LVTTL : : : Y
sel_addr1 : 43 : input : LVTTL : : : Y
sel_addr0 : 44 : input : LVTTL : : : Y
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