-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.0 (Build Build 168 06/22/2005)
-- Created on Mon Mar 06 11:11:13 2006

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY CLKCP IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		CLK : IN STD_LOGIC;
		CP : OUT STD_LOGIC;
		LP : OUT STD_LOGIC;
		FLM : OUT STD_LOGIC;
		DAT : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END CLKCP;


--  Architecture Body

ARCHITECTURE CLKCP_architecture OF CLKCP IS

VARIABLE a,b,c:INTEGER;

SIGNAL CPC,CPQ,LPQ,FLQ:STD_LOGIC;
BEGIN
PROCESS(CLK,LPQ,CPQ)
BEGIN

IF FLQ='1' THEN
 IF CLK'EVENT AND CLK='1' THEN  --每出現11個CLK發一個CPQ脈沖.
   IF a<12 THEN 
     a:=a+1;
     ELSE a:=0;
   END IF;
 END IF;
  IF a=5 THEN
    CPC<='1';
	ELSIF a=11 THEN
	CPC<='1';
    CPQ<='1';
	ELSE CPQ<='0';
	CPC<='0';
  END IF;

 IF CPQ'EVENT AND CPQ='1' THEN  --發送一行完成,發一個LP脈沖.
  IF b<=41 THEN 
	b:=b+1;
	ELSE b:=0;
  END IF;
 END IF;
  IF b=40 THEN
	LP<='1';
	ELSE LP<='0';
  END IF;
 FLQ<='0';

ELSE

IF CLK'EVENT AND CLK='1' THEN  --
   IF a<12 THEN 
     a:=a+1;
     ELSE a:=0;
   END IF;
 END IF;
 
 IF a=5 THEN
    CPC<='1';
	ELSIF a=11 THEN
	CPC<='1';
    CPQ<='1';
	ELSE CPQ<='0';
	CPC<='0';
  END IF;
 --IF a=11 THEN
	--CPQ<='1';
--	ELSE CPQ<='0';
 -- END IF;

 IF CPQ'EVENT AND CPQ='1' THEN  --
  IF b<41 THEN 
	b:=b+1;
	ELSE b:=0;
  END IF;
 END IF;
  IF b=40 THEN
	LPQ<='1';
	ELSE LPQ<='0';
  END IF;

  IF LPQ'EVENT AND LPQ='1' THEN
    IF c<240 THEN
      c:=c+1;
	ELSIF c=239 THEN
	 FLQ<='1';
	 c:=0;
	END IF;
  END IF;
END IF;

IF CPQ='1' THEN
  DAT<="0011";
END IF;



CP<=CPC;
LP<=LPQ;
FLM<=FLQ;



END  PROCESS;
END CLKCP_architecture;