library verilog;use verilog.vl_types.all;entity mux is    port(        \out\           : out    vl_logic_vector(7 downto 0);        rst             : in     vl_logic;        clk             : in     vl_logic;        cnt             : in     vl_logic_vector(4 downto 0);        d_in0           : in     vl_logic_vector(7 downto 0);        d_in1           : in     vl_logic_vector(7 downto 0);        d_in2           : in     vl_logic_vector(7 downto 0);        d_in3           : in     vl_logic_vector(7 downto 0);        d_in4           : in     vl_logic_vector(7 downto 0);        d_in5           : in     vl_logic_vector(7 downto 0);        d_in6           : in     vl_logic_vector(7 downto 0);        d_in7           : in     vl_logic_vector(7 downto 0);        d_in8           : in     vl_logic_vector(7 downto 0);        d_in9           : in     vl_logic_vector(7 downto 0);        d_in10          : in     vl_logic_vector(7 downto 0);        d_in11          : in     vl_logic_vector(7 downto 0);        d_in12          : in     vl_logic_vector(7 downto 0);        d_in13          : in     vl_logic_vector(7 downto 0);        d_in14          : in     vl_logic_vector(7 downto 0);        d_in15          : in     vl_logic_vector(7 downto 0);        d_in16          : in     vl_logic_vector(7 downto 0);        d_in17          : in     vl_logic_vector(7 downto 0);        d_in18          : in     vl_logic_vector(7 downto 0);        d_in19          : in     vl_logic_vector(7 downto 0);        d_in20          : in     vl_logic_vector(7 downto 0);        d_in21          : in     vl_logic_vector(7 downto 0);        d_in22          : in     vl_logic_vector(7 downto 0);        d_in23          : in     vl_logic_vector(7 downto 0);        d_in24          : in     vl_logic_vector(7 downto 0);        d_in25          : in     vl_logic_vector(7 downto 0);        d_in26          : in     vl_logic_vector(7 downto 0);        d_in27          : in     vl_logic_vector(7 downto 0);        d_in28          : in     vl_logic_vector(7 downto 0);        d_in29          : in     vl_logic_vector(7 downto 0);        d_in30          : in     vl_logic_vector(7 downto 0);        d_in31          : in     vl_logic_vector(7 downto 0)    );end mux;