-- VHDL Test Bench Created from source file lcdclk.vhd -- 17:37:02 04/26/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT lcdclk
	PORT(
		sysclk : IN std_logic;          
		clk_250khz : OUT std_logic;
		clk_50hz : OUT std_logic
		);
	END COMPONENT;

	SIGNAL sysclk :  std_logic;
	SIGNAL clk_250khz :  std_logic;
	SIGNAL clk_50hz :  std_logic;

BEGIN

	uut: lcdclk PORT MAP(
		sysclk => sysclk,
		clk_250khz => clk_250khz,
		clk_50hz => clk_50hz
	);

    PROCESS -- clock process for clk,
  BEGIN
		CLOCK_LOOP : LOOP

		sysclk <= transport '0';
		WAIT FOR 10 ns;
		sysclk <= transport '1';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		sysclk <= transport '0';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;




-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;