library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcdclk is
    Port ( sysclk : in std_logic;
           clk_250khz : out std_logic;
           clk_50hz : out std_logic);
end lcdclk;

architecture Behavioral of lcdclk is

signal clk_250khzbuf,clk_50hzbuf:std_logic;
signal counter_250khz :integer range 0 to 100;
signal counter_50hz :integer range 0 to 500000;
signal counter_ini :integer range 0 to 10;
begin

divclk:
process(sysclk)
begin
  if sysclk'event and sysclk='1' then
	 if counter_ini<=5 then
	   clk_250khzbuf<='1';
		clk_50hzbuf<='1';
		counter_ini<=counter_ini+1;
	 else
	   counter_ini<=6;	
		if counter_250khz=99 then
	     counter_250khz<=0;
		  clk_250khzbuf<=not clk_250khzbuf;
	   else
	     counter_250khz<=counter_250khz+1;
	   end if;

      if counter_50hz=499999 then
		  counter_50hz<=0;
		  clk_50hzbuf<=not clk_50hzbuf;
		else
		  counter_50hz<=counter_50hz+1;
		end if;
    end if;
  end if;
end process;

clk_250khz<=clk_250khzbuf;
clk_50hz<=clk_50hzbuf;

end Behavioral;