Release 5.2.03i - xst F.31Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.37 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.37 s | Elapsed : 0.00 / 1.00 s --> Reading design: lcdclk.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Low Level Synthesis  6) Final Report     6.1) Device utilization summary     6.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : lcdclk.prjInput Format                       : VHDLIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : lcdclkOutput Format                      : NGCTarget Device                      : xc2v1000-4fg456---- Source OptionsEntity Name                        : lcdclkAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESComplex Clock Enable Extraction    : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 16Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Criterion             : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : lowerTop module area constraint         : 100Top module allowed area overflow   : 5---- Other Optionsread_cores                         : YEScross_clock_analysis               : NO==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd in Library work.Entity <lcdclk> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <lcdclk> (Architecture <behavioral>).Entity <lcdclk> analyzed. Unit <lcdclk> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <lcdclk>.    Related source file is C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd.    Found 4-bit comparator lessequal for signal <$n0003> created at line 29.    Found 1-bit register for signal <clk_250khzbuf>.    Found 1-bit register for signal <clk_50hzbuf>.    Found 8-bit up counter for signal <counter_250khz>.    Found 20-bit up counter for signal <counter_50hz>.    Found 4-bit up counter for signal <counter_ini>.    Summary:	inferred   3 Counter(s).	inferred   2 D-type flip-flop(s).	inferred   1 Comparator(s).Unit <lcdclk> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 2  1-bit register                   : 2# Counters                         : 3  4-bit up counter                 : 1  8-bit up counter                 : 1  20-bit up counter                : 1# Comparators                      : 1  4-bit comparator lessequal       : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Library "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <lcdclk> ...Mapping all equations...Loading device for application Xst from file '2v1000.nph' in environment C:/Xilinx.Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block lcdclk, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : lcdclk.ngrTop Level Output File Name         : lcdclkOutput Format                      : NGCOptimization Criterion             : SpeedKeep Hierarchy                     : NOMacro Generator                    : macro+Design Statistics# IOs                              : 3Macro Statistics :# Registers                        : 5#      1-bit register              : 2#      20-bit register             : 3# Adders/Subtractors               : 3#      20-bit adder                : 3# Comparators                      : 1#      4-bit comparator lessequal  : 1Cell Usage :# BELS                             : 110#      GND                         : 1#      LUT1                        : 34#      LUT2                        : 2#      LUT3                        : 3#      LUT3_D                      : 1#      LUT4                        : 8#      LUT4_L                      : 1#      MUXCY                       : 29#      MUXF5                       : 1#      VCC                         : 1#      XORCY                       : 29# FlipFlops/Latches                : 34#      FDR                         : 2#      FDRE                        : 28#      FDS                         : 2#      FDSE                        : 2# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 2#      OBUF                        : 2=========================================================================Device utilization summary:---------------------------Selected Device : 2v1000fg456-4  Number of Slices:                      26  out of   5120     0%   Number of Slice Flip Flops:            34  out of  10240     0%   Number of 4 input LUTs:                49  out of  10240     0%   Number of bonded IOBs:                  2  out of    324     0%   Number of GCLKs:                        1  out of     16     6%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+sysclk                             | BUFGP                  | 34    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 6.856ns (Maximum Frequency: 145.858MHz)   Minimum input arrival time before clock: No path found   Maximum output required time after clock: 7.465ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'sysclk'Delay:               6.856ns (Levels of Logic = 3)  Source:            counter_ini_1  Destination:       counter_50hz_17  Source Clock:      sysclk rising  Destination Clock: sysclk rising  Data Path: counter_ini_1 to counter_50hz_17                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDS:c->q              4   0.568   1.069  counter_ini_1 (counter_ini_1)     LUT3_D:I0->O         16   0.439   1.692  _n00131 (_n0013)     LUT4:i0->o            1   0.439   0.000  _n00101_g (n1475)     MUXF5:i1->o          20   0.436   1.933  _n00101 (_n0010)     FDRE:r                    0.280          counter_50hz_17    ----------------------------------------    Total                      6.856ns (2.162ns logic, 4.694ns route)                                       (31.5% logic, 68.5% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'sysclk'Offset:              7.465ns (Levels of Logic = 1)  Source:            clk_50hzbuf  Destination:       clk_50hz  Source Clock:      sysclk rising  Data Path: clk_50hzbuf to clk_50hz                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDSE:c->q             2   0.568   0.790  clk_50hzbuf (clk_50hzbuf)     OBUF:i->o                 6.107          clk_50hz_obuf (clk_50hz)    ----------------------------------------    Total                      7.465ns (6.675ns logic, 0.790ns route)                                       (89.4% logic, 10.6% route)=========================================================================CPU : 4.68 / 5.34 s | Elapsed : 5.00 / 6.00 s --> Total memory usage is 72600 kilobytes