Release 6.1i - xst G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s --> Reading design: krtlcd.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : krtlcd.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : krtlcdOutput Format                      : NGCTarget Device                      : xc2s300e-6-fg456---- Source OptionsTop Module Name                    : krtlcdAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : krtlcd.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NO==================================================================================================================================================*                          HDL Compilation                              *=========================================================================WARNING:HDLParsers:3215 - Unit work/KRTLCD is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/krtlcd.vhd, now is C:/lcd_new300/krtlcd/krtlcd.vhdWARNING:HDLParsers:3215 - Unit work/KRTLCD/BEHAVIORAL is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/krtlcd.vhd, now is C:/lcd_new300/krtlcd/krtlcd.vhdWARNING:HDLParsers:3215 - Unit work/LCDKEY is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/lcdkey.vhd, now is C:/lcd_new300/krtlcd/lcdkey.vhdWARNING:HDLParsers:3215 - Unit work/LCDKEY/BEHAVIORAL is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/lcdkey.vhd, now is C:/lcd_new300/krtlcd/lcdkey.vhdWARNING:HDLParsers:3215 - Unit work/LCDCLK is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd, now is C:/lcd_new300/krtlcd/lcdclk.vhdWARNING:HDLParsers:3215 - Unit work/LCDCLK/BEHAVIORAL is now defined in a different file: was C:/Xilinx/HLDexamples/krtlcd/lcdclk.vhd, now is C:/lcd_new300/krtlcd/lcdclk.vhdCompiling vhdl file C:/lcd_new300/krtlcd/lcdclk.vhd in Library work.Entity <lcdclk> (Architecture <Behavioral>) compiled.Compiling vhdl file C:/lcd_new300/krtlcd/lcdkey.vhd in Library work.Entity <lcdkey> (Architecture <Behavioral>) compiled.Compiling vhdl file C:/lcd_new300/krtlcd/krtlcd.vhd in Library work.Entity <krtlcd> (Architecture <Behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <krtlcd> (Architecture <Behavioral>).Entity <krtlcd> analyzed. Unit <krtlcd> generated.Analyzing Entity <lcdclk> (Architecture <behavioral>).Entity <lcdclk> analyzed. Unit <lcdclk> generated.Analyzing Entity <lcdkey> (Architecture <behavioral>).Entity <lcdkey> analyzed. Unit <lcdkey> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <lcdkey>.    Related source file is C:/lcd_new300/krtlcd/lcdkey.vhd.    Found 29-bit comparator greatequal for signal <$n0007> created at line 39.    Found 29-bit up counter for signal <counter>.    Found 1-bit register for signal <lightbuf>.    Found 2-bit up counter for signal <modebuf>.    Found 16-bit register for signal <shiftlightkey>.    Found 16-bit register for signal <shiftmodekey>.    Summary:	inferred   2 Counter(s).	inferred  33 D-type flip-flop(s).	inferred   1 Comparator(s).Unit <lcdkey> synthesized.Synthesizing Unit <lcdclk>.    Related source file is C:/lcd_new300/krtlcd/lcdclk.vhd.    Found 4-bit comparator lessequal for signal <$n0003> created at line 29.    Found 1-bit register for signal <clk_250khzbuf>.    Found 1-bit register for signal <clk_50hzbuf>.    Found 7-bit up counter for signal <counter_250khz>.    Found 19-bit up counter for signal <counter_50hz>.    Found 4-bit up counter for signal <counter_ini>.    Summary:	inferred   3 Counter(s).	inferred   2 D-type flip-flop(s).	inferred   1 Comparator(s).Unit <lcdclk> synthesized.Synthesizing Unit <krtlcd>.    Related source file is C:/lcd_new300/krtlcd/krtlcd.vhd.WARNING:Xst:1780 - Signal <count50hz> is never used or assigned.WARNING:Xst:646 - Signal <clk_50hz> is assigned but never used.    Found 1024x8-bit ROM for signal <$n0014> created at line 167.    Found 1024x8-bit ROM for signal <$n0015> created at line 168.    Found 1024x8-bit ROM for signal <$n0016> created at line 169.    Found 1024x8-bit ROM for signal <$n0017> created at line 170.    Found finite state machine <FSM_0> for signal <present_state>.    -----------------------------------------------------------------------    | States             | 2                                              |    | Transitions        | 10                                             |    | Inputs             | 8                                              |    | Outputs            | 2                                              |    | Clock              | clk_250khz (falling_edge)                      |    | Power Up State     | initial                                        |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <lcd_di>.    Found 1-bit register for signal <lcd_cs1>.    Found 1-bit register for signal <lcd_cs2>.    Found 4-bit adder for signal <$n0041> created at line 141.    Found 10-bit adder for signal <$n0046> created at line 176.    Found 3-bit adder for signal <$n0047>.    Found 10-bit register for signal <addrbuf>.    Found 4-bit register for signal <counter_ini>.    Found 3-bit register for signal <counterbuf>.    Found 8-bit register for signal <dbbuf>.    Found 1-bit register for signal <ebuf>.    Summary:	inferred   1 Finite State Machine(s).	inferred   4 ROM(s).	inferred  29 D-type flip-flop(s).	inferred   3 Adder/Subtracter(s).Unit <krtlcd> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# FSMs                             : 1# ROMs                             : 4  1024x8-bit ROM                   : 4# Registers                        : 43  1-bit register                   : 39  4-bit register                   : 1  8-bit register                   : 1  10-bit register                  : 1  3-bit register                   : 1# Counters                         : 5  29-bit up counter                : 1  2-bit up counter                 : 1  4-bit up counter                 : 1  7-bit up counter                 : 1  19-bit up counter                : 1# Adders/Subtractors               : 3  4-bit adder                      : 1  10-bit adder                     : 1  3-bit adder                      : 1# Comparators                      : 2  29-bit comparator greatequal     : 1  4-bit comparator lessequal       : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *=========================================================================INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <present_state> with one-hot encoding.=========================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:1291 - FF/Latch <clk_50hzbuf> is unconnected in block <U0>.Optimizing unit <krtlcd> ...Optimizing unit <lcdclk> ...Optimizing unit <lcdkey> ...Loading device for application Xst from file '2s300e.nph' in environment C:/Xilinx.Mapping all equations...WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_17> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_clk_50hzbuf> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_18> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_0> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_1> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_2> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_3> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_4> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_5> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_6> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_7> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_8> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_9> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_10> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_11> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_12> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_13> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_14> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_15> is unconnected in block <krtlcd>.WARNING:Xst:1291 - FF/Latch <U0_counter_50hz_16> is unconnected in block <krtlcd>.Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block krtlcd, actual ratio is 30.FlipFlop addrbuf_7 has been replicated 6 time(s)FlipFlop addrbuf_6 has been replicated 9 time(s)FlipFlop addrbuf_5 has been replicated 18 time(s)FlipFlop addrbuf_4 has been replicated 33 time(s)FlipFlop addrbuf_0 has been replicated 50 time(s)FlipFlop addrbuf_1 has been replicated 50 time(s)FlipFlop addrbuf_3 has been replicated 53 time(s)FlipFlop addrbuf_2 has been replicated 52 time(s)FlipFlop addrbuf_8 has been replicated 4 time(s)FlipFlop present_state_FFd1 has been replicated 1 time(s)FlipFlop addrbuf_9 has been replicated 1 time(s)FlipFlop U0_clk_250khzbuf has been replicated 3 time(s)=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : krtlcd.ngrTop Level Output File Name         : krtlcdOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 19Macro Statistics :# ROMs                             : 4#      1024x8-bit ROM              : 4# Registers                        : 48