Release 6.1i Map G.26Xilinx Mapping Report File for Design 'krtlcd'Design Information------------------Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s300e-fg456-6 -cm
area -pr b -k 4 -c 100 -tx off -o krtlcd_map.ncd krtlcd.ngd krtlcd.pcf Target Device  : x2s300eTarget Package : fg456Target Speed   : -6Mapper Version : spartan2e -- $Revision: 1.16 $Mapped Date    : Fri Jun 11 14:14:30 2004Design Summary--------------Number of errors:      0Number of warnings:    1Logic Utilization:  Number of Slice Flip Flops:       384 out of  6,144    6%  Number of 4 input LUTs:         1,520 out of  6,144   24%Logic Distribution:    Number of occupied Slices:                       1,071 out of  3,072   34%    Number of Slices containing only related logic:  1,071 out of  1,071  100%    Number of Slices containing unrelated logic:         0 out of  1,071    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:        1,584 out of  6,144   25%      Number used as logic:                     1,520      Number used as a route-thru:                 64   Number of bonded IOBs:            18 out of    325    5%      IOB Flip Flops:                               3   Number of GCLKs:                   1 out of      4   25%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  15,759Additional JTAG gate count for IOBs:  912Peak Memory Usage:  79 MBNOTES:   Related logic is defined as being logic that shares connectivity -   e.g. two LUTs are "related" if they share common inputs.   When assembling slices, Map gives priority to combine logic that   is related.  Doing so results in the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin   packing unrelated logic into a slice once 99% of the slices are   occupied through related logic packing.   Note that once logic distribution reaches the 99% level through   related logic packing, this does not mean the device is completely   utilized.  Unrelated logic packing will then begin, continuing until   all usable LUTs and FFs are occupied.  Depending on your timing   budget, increased levels of unrelated logic packing may adversely   affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:Pack:267 - The F6 multiplexer Mrom__n0017_inst_mux_f6_420 failed to
   merge with F5 multiplexer Mrom__n0017_inst_mux_f5_748.  There is a conflict
   for the GYMUX.  The design will exhibit suboptimal timing.Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| sysclk                             | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || lcd_cs1                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_cs2                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_data<0>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_data<1>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_data<2>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_data<3>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_data<4>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_data<5>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_data<6>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_data<7>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_di                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || lcd_dir                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_e                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_k                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_lightkey                       | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || lcd_modekey                        | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || lcd_rst                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lcd_rw                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 19Number of Equivalent Gates for Design = 15,759Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 78IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 3IOB Flip Flops = 3Unbonded IOBs = 0Bonded IOBs = 18Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 10554 input LUTs used as Route-Thrus = 644 input LUTs = 1520Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 75Slice Flip Flops = 384Slices = 1071Number of LUT signals with 4 loads = 2Number of LUT signals with 3 loads = 1Number of LUT signals with 2 loads = 14Number of LUT signals with 1 load = 1476NGM Average fanout of LUT = 1.26NGM Maximum fanout of LUT = 51NGM Average fanin for LUT = 3.6678Number of LUT symbols = 1520Number of IPAD symbols = 3Number of IBUF symbols = 2