library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vga is
    Port (clk:in std_logic;
    		rst:in std_logic;
		hs:buffer std_logic;
		vs:buffer std_logic;
		hloc:out std_logic_vector(9 downto 0);
		vloc:out std_logic_vector(9 downto 0));
end vga;

architecture Behavioral of vga is
signal vgaclk:std_logic;
signal hlocbuf,vlocbuf:std_logic_vector(9 downto 0);
begin

hloc<=hlocbuf;
vloc<=vlocbuf;

process(clk)
begin
  if clk'event and clk='1' then
    vgaclk<=not vgaclk;
  end if;
end process;

process(rst,vgaclk)
begin
  if rst='0' then
    hlocbuf<="0000000000";
    vlocbuf<="0000000000";
  else
    if vgaclk'event and vgaclk='1' then
    hlocbuf<=hlocbuf+1;
    if hlocbuf=799 then
      hlocbuf<="0000000000";
    end if;
    end if;
    if hs'event and hs='1' then
      vlocbuf<=vlocbuf+1;
	 if vlocbuf=524 then
	   vlocbuf<="0000000000";
	 end if;
    end if;
  end if;
end process;

process(hlocbuf,vlocbuf)
begin
  if hlocbuf>=656 and hlocbuf<752 then
    hs<='0';
  else
    hs<='1';
  end if;
  if vlocbuf>=499 and vlocbuf<501 then
    vs<='0';
  else
    vs<='1';
  end if;
end process;

end Behavioral;