/////////////////////////////////////////////////////////////////////
////                                                             ////
////  vsr_4_03	rx state machine				 ////
////                                                             ////
////  Author: liyu	                                         ////
////          acousticdream@163.com                              ////
////          		                                         ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2004 liyu                        		 ////
////                    acousticdream@163.com                    ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vsr_4_3_rx_state(
		ch0_pattern,
		ch1_pattern,
		ch2_pattern,
		ch3_pattern,
		ch0_oof,
		ch1_oof,
		ch2_oof,
		ch3_oof,
		sync_state,
		clk0,
		clk1,
		clk2,
		clk3,
		rst,
		);
parameter	NO_SYNC=3'b000,
		AC_SYNC=3'b001,
		RE_SYNC=3'b010,
		IN_SYNC=3'b100;
		
input	ch0_pattern;
input	ch1_pattern;
input	ch2_pattern;
input	ch3_pattern;
input	ch0_oof;
input	ch1_oof;
input	ch2_oof;
input	ch3_oof;
input	rst;
input	clk0;
input	clk1;
input	clk2;
input	clk3;

output	[2:0]	sync_state;

reg	[2:0]	sync_state;
reg	[3:0]	ch0_pattern_delay;
reg	[3:0]	ch1_pattern_delay;
reg	[3:0]	ch2_pattern_delay;
reg	[3:0]	ch3_pattern_delay;

wire	ch0_deskew_window=(ch0_pattern_delay)?1'b1:1'b0;
wire	ch1_deskew_window=(ch1_pattern_delay)?1'b1:1'b0;
wire	ch2_deskew_window=(ch2_pattern_delay)?1'b1:1'b0;
wire	ch3_deskew_window=(ch3_pattern_delay)?1'b1:1'b0;

wire	fp_on_one_ch=ch0_deskew_window|ch1_deskew_window|ch2_deskew_window|ch3_deskew_window;
wire	fp_on_all_ch=ch0_deskew_window&ch1_deskew_window&ch2_deskew_window&ch3_deskew_window;

always@(posedge clk0 or posedge rst)
begin
	if (rst)
		ch0_pattern_delay<=4'b0000;
	else begin
		ch0_pattern_delay[0]<=ch0_pattern;
		ch0_pattern_delay[3:1]<=ch0_pattern_delay[2:0];
	end		
end	

always@(posedge clk1 or posedge rst)
begin
	if (rst)
		ch1_pattern_delay<=4'b0000;
	else begin
		ch1_pattern_delay[0]<=ch1_pattern;
		ch1_pattern_delay[3:1]<=ch1_pattern_delay[2:0];
	end		
end

always@(posedge clk2 or posedge rst)
begin
	if (rst)
		ch2_pattern_delay<=4'b0000;
	else begin
		ch2_pattern_delay[0]<=ch2_pattern;
		ch2_pattern_delay[3:1]<=ch2_pattern_delay[2:0];
	end		
end

always@(posedge clk3 or posedge rst)
begin
	if (rst)
		ch3_pattern_delay<=4'b0000;
	else begin
		ch3_pattern_delay[0]<=ch3_pattern;
		ch3_pattern_delay[3:1]<=ch3_pattern_delay[2:0];
	end		
end

always@(posedge clk0 or posedge rst)
begin
	if (rst)
		sync_state<=NO_SYNC;
	else begin
		case(sync_state)
		NO_SYNC: begin
			if (fp_on_one_ch)
				sync_state<=AC_SYNC;
		end	
		AC_SYNC: begin
			if (fp_on_all_ch)
				sync_state<=RE_SYNC;
			if (!fp_on_one_ch)
				sync_state<=NO_SYNC;
		end
		RE_SYNC: begin
			if (ch0_oof|ch1_oof|ch2_oof|ch3_oof)
				sync_state<=NO_SYNC;
			else
				sync_state<=IN_SYNC;					
		end				
		IN_SYNC: begin
			if (ch0_oof|ch1_oof|ch2_oof|ch3_oof)
				sync_state<=NO_SYNC;
		end	
		endcase
	end		
end	
		
endmodule