/////////////////////////////////////////////////////////////////////
////                                                             ////
////  vsr_4_03	4 stages data select			         ////
////                                                             ////
////  Author: liyu	                                         ////
////          acousticdream@163.com                              ////
////          		                                         ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2004 liyu                        		 ////
////                    acousticdream@163.com                    ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//synopsys translate_off
`include "timescale.v"
//synopsys translate_on

module vsr_4_3_rx_data_path(din,dout,clk,sel);
input	[15:0]	din;
output	[15:0]	dout;
input		clk;
input	[3:0]	sel;



reg	[7:0] 	reg3a;
reg	[15:0]	reg3;
wire	[15:0]	sub_wire3;

always@(posedge clk)
begin
	reg3<=din;
	reg3a<=reg3[7:0];
end	
	
vsr_4_3_mux2_1	shifter3(.din({reg3a,reg3}),.dout(sub_wire3),.sel(sel[3]));
defparam	shifter3.WIDTH=16,
          	shifter3.ORIGNAL=24;

reg	[3:0] 	reg4a;
reg	[15:0]	reg4;
wire	[15:0]	sub_wire4;

always@(posedge clk)
begin
	reg4<=sub_wire3;
	reg4a<=reg4[3:0];
end	
	
vsr_4_3_mux2_1	shifter4(.din({reg4a,reg4}),.dout(sub_wire4),.sel(sel[2]));
defparam	shifter4.WIDTH=16,
          	shifter4.ORIGNAL=20;

reg	[1:0] 	reg5a;
reg	[15:0]	reg5;
wire	[15:0]	sub_wire5;

always@(posedge clk)
begin
	reg5<=sub_wire4;
	reg5a<=reg5[1:0];
end	
	
vsr_4_3_mux2_1	shifter5(.din({reg5a,reg5}),.dout(sub_wire5),.sel(sel[1]));
defparam	shifter5.WIDTH=16,
          	shifter5.ORIGNAL=18;
     	
reg		reg6a;
reg	[15:0]	reg6;
wire	[15:0]	sub_wire6;

always@(posedge clk)
begin
	reg6<=sub_wire5;
	reg6a<=reg6[0];
end	
	
vsr_4_3_mux2_1	shifter6(.din({reg6a,reg6}),.dout(sub_wire6),.sel(sel[0]));
defparam	shifter6.WIDTH=16,
          	shifter6.ORIGNAL=17;
   	
assign	dout=sub_wire6;

endmodule