/////////////////////////////////////////////////////////////////////
////                                                             ////
////  vsr_4_03	rx deskew buffer				 ////
////                                                             ////
////  Author: liyu	                                         ////
////          acousticdream@163.com                              ////
////          		                                         ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2004 liyu                        		 ////
////                    acousticdream@163.com                    ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vsr_4_3_alignment_buffer(
		din0,
		din1,
		din2,
		din3,
		fr0,
		fr1,
		fr2,
		fr3,
		syn_state,
		dout,
		clk0,
		clk1,
		clk2,
		clk3,
		rst
		);
input	[15:0]	din0;
input	[15:0]	din1;
input	[15:0]	din2;
input	[15:0]	din3;
input		fr0;
input		fr1;
input		fr2;
input		fr3;
input	[2:0]	syn_state;
input		clk0;
input		clk1;
input		clk2;
input		clk3;
input		rst;
output	[63:0]	dout;

wire		all_sync=(syn_state==3'b100)?1'b1:1'b0;

reg	[15:0]	buffer0	[7:0];
reg	[15:0]	buffer1	[7:0];
reg	[15:0]	buffer2	[7:0];
reg	[15:0]	buffer3	[7:0];
reg	[2:0]	waddr0;
reg	[2:0]	waddr1;
reg	[2:0]	waddr2;
reg	[2:0]	waddr3;
reg	[2:0]	raddr;

wire	[63:0]	dout;

always@(posedge clk0 or posedge rst)
begin
	if (rst)
		waddr0<=3'b000;
	else begin
		if (fr0||waddr0==3'b111)
			waddr0<=3'b000;
		else 
			waddr0<=waddr0+3'b001;			
	end	
end	

always@(posedge clk1 or posedge rst)
begin
	if (rst)
		waddr1<=3'b000;
	else begin
		if (fr1||waddr1==3'b111)
			waddr1<=3'b000;
		else 
			waddr1<=waddr1+3'b001;			
	end	
end	

always@(posedge clk2 or posedge rst)
begin
	if (rst)
		waddr2<=3'b000;
	else begin
		if (fr2||waddr2==3'b111)
			waddr2<=3'b000;
		else 
			waddr2<=waddr2+3'b001;			
	end	
end	

always@(posedge clk3 or posedge rst)
begin
	if (rst)
		waddr3<=3'b000;
	else begin
		if (fr3||waddr3==3'b111)
			waddr3<=3'b000;
		else 
			waddr3<=waddr3+3'b001;			
	end	
end	

always@(posedge clk0)
begin
	buffer0[waddr0]<=din0;
end	

always@(posedge clk1)
begin
	buffer1[waddr1]<=din1;
end	

always@(posedge clk2)
begin
	buffer2[waddr2]<=din2;
end	


always@(posedge clk3)
begin
	buffer3[waddr3]<=din3;
end		

always@(posedge clk0 or posedge rst)
begin
	if (rst)
		raddr<=3'b000;
	else begin
		if (fr0)
			raddr<=3'b100;
		else begin
			if (raddr==3'b111)
				raddr<=3'b000;
			else	
				raddr<=raddr+3'b001;	
		end				
	end	
end		
		
assign	dout={buffer0[raddr],buffer1[raddr],buffer2[raddr],buffer3[raddr]};		
endmodule