library verilog;use verilog.vl_types.all;entity level is    port(        o               : out    vl_logic;        s               : out    vl_logic;        i1_o            : in     vl_logic;        i1_s            : in     vl_logic;        i0_o            : in     vl_logic;        i0_s            : in     vl_logic    );end level;