?? 87_control_stim.vhd

?? 有關于VHDL舉例,FPGA/CPLD的運用方面的例子
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--------------------------------------------------------------------------------
--
--   AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source:  AMD data book
--
--------------------------------------------------------------------------------

library l2901_lib;
use l2901_lib.types.all;
use l2901_lib.MVL7_functions.all;	--some binary functions
use l2901_lib.synthesis_types.all;	--hints for synthesis

entity E is
end;

architecture AA of E is
	 component ccontrol
	  port (
		I : in MVL7_VECTOR(3 downto 0);
		CCEN_BAR : in MVL7;
		CC_BAR : in MVL7;
		Rzero_bar : in MVL7;
		PL_BAR : out MVL7;
		VECT_BAR : out MVL7;
		MAP_BAR : out MVL7;
		R_sel : out MVL7;
		D_sel : out MVL7;
		uPC_sel : out MVL7;
		stack_sel : out MVL7;
		decr : out MVL7;
		load : out MVL7;
		clear : out MVL7;
		push : out MVL7;
		pop : out MVL7
	  );
	 end component;

		signal I : MVL7_VECTOR(3 downto 0);
		signal CCEN_BAR : MVL7;
		signal CC_BAR : MVL7;
		signal Rzero_bar : MVL7;
		signal PL_BAR : MVL7;
		signal VECT_BAR : MVL7;
		signal MAP_BAR : MVL7;
		signal R_sel : MVL7;
		signal D_sel : MVL7;
		signal uPC_sel : MVL7;
		signal stack_sel : MVL7;
		signal decr : MVL7;
		signal load : MVL7;
		signal clear : MVL7;
		signal push : MVL7;
		signal pop : MVL7;
for all : ccontrol use entity work.control(control);

begin

CCONTROL1 : ccontrol port map(
		I,
		CCEN_BAR,
		CC_BAR,
		Rzero_bar,
		PL_BAR,
		VECT_BAR,
		MAP_BAR,
		R_sel,
		D_sel,
		uPC_sel,
		stack_sel,
		decr,
		load,
		clear,
		push,
		pop
           );

process

begin

-- *********
-- * I = 0 *
-- *********
--------------------------

I <= "0000";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';

wait for 1 ns; --	 Cycle No: 0

assert (PL_BAR = '0')
report
"Assert 0 : < PL_BAR /= 0 >" -- 	Vector No: 0
severity warning;

assert (VECT_BAR = '1')
report
"Assert 1 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 2 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 3 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 4 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '0')
report
"Assert 5 : < uPC_sel /= 0 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 6 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 7 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 8 : < load /= 0 >"
severity warning;

assert (clear = '1')
report
"Assert 9 : < clear /= 1 >"
severity warning;

assert (push = '0')
report
"Assert 10 : < push /= 0 >"
severity warning;

assert (pop = '0')
report
"Assert 11 : < pop /= 0 >"
severity warning;

wait for 1 ns;

--------------------------

I <= "0000";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';

wait for 1 ns; --	 Cycle No: 1

assert (PL_BAR = '0')
report
"Assert 12 : < PL_BAR /= 0 >" -- 	Vector No: 1
severity warning;

assert (VECT_BAR = '1')
report
"Assert 13 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 14 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 15 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 16 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '0')
report
"Assert 17 : < uPC_sel /= 0 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 18 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 19 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 20 : < load /= 0 >"
severity warning;

assert (clear = '1')
report
"Assert 21 : < clear /= 1 >"
severity warning;

assert (push = '0')
report
"Assert 22 : < push /= 0 >"
severity warning;

assert (pop = '0')
report
"Assert 23 : < pop /= 0 >"
severity warning;

wait for 1 ns;

-- ***********************************
--------------------------

I <= "0000";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';

wait for 1 ns; --	 Cycle No: 2

assert (PL_BAR = '0')
report
"Assert 24 : < PL_BAR /= 0 >" -- 	Vector No: 2
severity warning;

assert (VECT_BAR = '1')
report
"Assert 25 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 26 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 27 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 28 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '0')
report
"Assert 29 : < uPC_sel /= 0 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 30 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 31 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 32 : < load /= 0 >"
severity warning;

assert (clear = '1')
report
"Assert 33 : < clear /= 1 >"
severity warning;

assert (push = '0')
report
"Assert 34 : < push /= 0 >"
severity warning;

assert (pop = '0')
report
"Assert 35 : < pop /= 0 >"
severity warning;

wait for 1 ns;

--------------------------

I <= "0000";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';

wait for 1 ns; --	 Cycle No: 3

assert (PL_BAR = '0')
report
"Assert 36 : < PL_BAR /= 0 >" -- 	Vector No: 3
severity warning;

assert (VECT_BAR = '1')
report
"Assert 37 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 38 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 39 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 40 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '0')
report
"Assert 41 : < uPC_sel /= 0 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 42 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 43 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 44 : < load /= 0 >"
severity warning;

assert (clear = '1')
report
"Assert 45 : < clear /= 1 >"
severity warning;

assert (push = '0')
report
"Assert 46 : < push /= 0 >"
severity warning;

assert (pop = '0')
report
"Assert 47 : < pop /= 0 >"
severity warning;

wait for 1 ns;

-- ***********************************
--------------------------

I <= "0000";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';

wait for 1 ns; --	 Cycle No: 4

assert (PL_BAR = '0')
report
"Assert 48 : < PL_BAR /= 0 >" -- 	Vector No: 4
severity warning;

assert (VECT_BAR = '1')
report
"Assert 49 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 50 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 51 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 52 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '0')
report
"Assert 53 : < uPC_sel /= 0 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 54 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 55 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 56 : < load /= 0 >"
severity warning;

assert (clear = '1')
report
"Assert 57 : < clear /= 1 >"
severity warning;

assert (push = '0')
report
"Assert 58 : < push /= 0 >"
severity warning;

assert (pop = '0')
report
"Assert 59 : < pop /= 0 >"
severity warning;

wait for 1 ns;

--------------------------

I <= "0000";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';

wait for 1 ns; --	 Cycle No: 5

assert (PL_BAR = '0')
report
"Assert 60 : < PL_BAR /= 0 >" -- 	Vector No: 5
severity warning;

assert (VECT_BAR = '1')
report
"Assert 61 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 62 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 63 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 64 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '0')
report
"Assert 65 : < uPC_sel /= 0 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 66 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 67 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 68 : < load /= 0 >"
severity warning;

assert (clear = '1')
report
"Assert 69 : < clear /= 1 >"
severity warning;

assert (push = '0')
report
"Assert 70 : < push /= 0 >"
severity warning;

assert (pop = '0')
report
"Assert 71 : < pop /= 0 >"
severity warning;

wait for 1 ns;

-- ***********************************
--------------------------

I <= "0000";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';

wait for 1 ns; --	 Cycle No: 6

assert (PL_BAR = '0')
report
"Assert 72 : < PL_BAR /= 0 >" -- 	Vector No: 6
severity warning;

assert (VECT_BAR = '1')
report
"Assert 73 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 74 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 75 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 76 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '0')
report
"Assert 77 : < uPC_sel /= 0 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 78 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 79 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 80 : < load /= 0 >"
severity warning;

assert (clear = '1')
report
"Assert 81 : < clear /= 1 >"
severity warning;

assert (push = '0')
report
"Assert 82 : < push /= 0 >"
severity warning;

assert (pop = '0')
report
"Assert 83 : < pop /= 0 >"
severity warning;

wait for 1 ns;

--------------------------

I <= "0000";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';

wait for 1 ns; --	 Cycle No: 7

assert (PL_BAR = '0')
report
"Assert 84 : < PL_BAR /= 0 >" -- 	Vector No: 7
severity warning;

assert (VECT_BAR = '1')
report
"Assert 85 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 86 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 87 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 88 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '0')
report
"Assert 89 : < uPC_sel /= 0 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 90 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 91 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 92 : < load /= 0 >"
severity warning;

assert (clear = '1')
report
"Assert 93 : < clear /= 1 >"
severity warning;

assert (push = '0')
report
"Assert 94 : < push /= 0 >"
severity warning;

assert (pop = '0')
report
"Assert 95 : < pop /= 0 >"
severity warning;

wait for 1 ns;

-- ***********************************
-- *********
-- * I = 1 *
-- *********
--------------------------

I <= "0001";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';

wait for 1 ns; --	 Cycle No: 8

assert (PL_BAR = '0')
report
"Assert 96 : < PL_BAR /= 0 >" -- 	Vector No: 8
severity warning;

assert (VECT_BAR = '1')
report
"Assert 97 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 98 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 99 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 100 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '1')
report
"Assert 101 : < uPC_sel /= 1 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 102 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 103 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 104 : < load /= 0 >"
severity warning;

assert (clear = '0')
report
"Assert 105 : < clear /= 0 >"
severity warning;

assert (push = '0')
report
"Assert 106 : < push /= 0 >"
severity warning;

assert (pop = '0')
report
"Assert 107 : < pop /= 0 >"
severity warning;

wait for 1 ns;

--------------------------

I <= "0001";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';

wait for 1 ns; --	 Cycle No: 9

assert (PL_BAR = '0')
report
"Assert 108 : < PL_BAR /= 0 >" -- 	Vector No: 9
severity warning;

assert (VECT_BAR = '1')
report
"Assert 109 : < VECT_BAR /= 1 >"
severity warning;

assert (MAP_BAR = '1')
report
"Assert 110 : < MAP_BAR /= 1 >"
severity warning;

assert (R_sel = '0')
report
"Assert 111 : < R_sel /= 0 >"
severity warning;

assert (D_sel = '0')
report
"Assert 112 : < D_sel /= 0 >"
severity warning;

assert (uPC_sel = '1')
report
"Assert 113 : < uPC_sel /= 1 >"
severity warning;

assert (stack_sel = '0')
report
"Assert 114 : < stack_sel /= 0 >"
severity warning;

assert (decr = '0')
report
"Assert 115 : < decr /= 0 >"
severity warning;

assert (load = '0')
report
"Assert 116 : < load /= 0 >"
severity warning;

assert (clear = '0')
report
"Assert 117 : < clear /= 0 >"
severity warning;
12 3 4 5 下一頁
?? 文件大小 195 K
?? 上傳用戶 leeixndong
?? 所屬分類 VHDL/FPGA/Verilog
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?? 87_control_stim.vhd

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