{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 04 15:13:59 2005 " "Info: Processing started: Fri Nov 04 15:13:59 2005" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off isa_lpt -c isa_lpt --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off isa_lpt -c isa_lpt --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[0\] " "Info: Assuming node \"ISA_A\[0\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[0\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[1\] " "Info: Assuming node \"ISA_A\[1\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[1\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_AEN " "Info: Assuming node \"ISA_AEN\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 18 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_AEN" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[3\] " "Info: Assuming node \"ISA_A\[3\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[3\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[14\] " "Info: Assuming node \"ISA_A\[14\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[14\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[8\] " "Info: Assuming node \"ISA_A\[8\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[8\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[19\] " "Info: Assuming node \"ISA_A\[19\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[19\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[9\] " "Info: Assuming node \"ISA_A\[9\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[9\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[13\] " "Info: Assuming node \"ISA_A\[13\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[13\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[16\] " "Info: Assuming node \"ISA_A\[16\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[16\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[10\] " "Info: Assuming node \"ISA_A\[10\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[10\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[2\] " "Info: Assuming node \"ISA_A\[2\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[2\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[4\] " "Info: Assuming node \"ISA_A\[4\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[4\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[18\] " "Info: Assuming node \"ISA_A\[18\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[18\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[17\] " "Info: Assuming node \"ISA_A\[17\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[17\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[11\] " "Info: Assuming node \"ISA_A\[11\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[11\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[15\] " "Info: Assuming node \"ISA_A\[15\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[15\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[7\] " "Info: Assuming node \"ISA_A\[7\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[7\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[6\] " "Info: Assuming node \"ISA_A\[6\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[6\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[12\] " "Info: Assuming node \"ISA_A\[12\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[12\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_A\[5\] " "Info: Assuming node \"ISA_A\[5\]\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 14 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_A\[5\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ISA_IOW " "Info: Assuming node \"ISA_IOW\" is an undefined clock" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 16 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ISA_IOW" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "LPT_DATA_CS~1 " "Info: Detected gated clock \"LPT_DATA_CS~1\" as buffer" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 40 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LPT_DATA_CS~1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LPT_ACK_CS~158 " "Info: Detected gated clock \"LPT_ACK_CS~158\" as buffer" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 43 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LPT_ACK_CS~158" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LPT_ACK_CS~156 " "Info: Detected gated clock \"LPT_ACK_CS~156\" as buffer" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 43 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LPT_ACK_CS~156" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LPT_ACK_CS~155 " "Info: Detected gated clock \"LPT_ACK_CS~155\" as buffer" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 43 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LPT_ACK_CS~155" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LPT_ACK_CS~154 " "Info: Detected gated clock \"LPT_ACK_CS~154\" as buffer" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 43 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LPT_ACK_CS~154" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LPT_ACK_CS~153 " "Info: Detected gated clock \"LPT_ACK_CS~153\" as buffer" {  } { { "isa_lpt.v" "" { Text "D:/evoc/lptb/isa_lpt.v" 43 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LPT_ACK_CS~153" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ISA_A\[0\] " "Info: No valid register-to-register data paths exist for clock \"ISA_A\[0\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ISA_A\[1\] " "Info: No valid register-to-register data paths exist for clock \"ISA_A\[1\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ISA_AEN " "Info: No valid register-to-register data paths exist for clock \"ISA_AEN\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ISA_A\[3\] " "Info: No valid register-to-register data paths exist for clock \"ISA_A\[3\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}