LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADD8B IS 
   PORT 
       ( A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         C : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) );
END ADD8B;
ARCHITECTURE HDLARCH OF ADD8B IS
COMPONENT ADD IS
PORT (AIN,BIN,CIN :IN STD_LOGIC;
          COUNT,SUM  : OUT STD_LOGIC);
END COMPONENT;
SIGNAL STMP : STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN 
STMP(0)<='0';C(8)<=STMP(8);
GENSUB :FOR I IN 0 TO 7 GENERATE
U1 : ADD PORT MAP(AIN=>A(I),BIN=>B(I),CIN =>STMP(I),SUM=>C(I),COUNT=>STMP(I+1));
END GENERATE;
END;