?? start.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity START is
port ( CON_EN:in std_logic;
CON:out std_logic);
end;
architecture BEHV of START is
signal qq:std_logic;
begin
process(cON_EN)
begin
if CON_EN'event and CON_EN='1' then
QQ<=NOT QQ;
end if;
CON<=QQ;
end process;
end;
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