library ieee;
use ieee.std_logic_1164.all;
 entity show is
port(di:in integer range 0 to 9;
     a,b,c,d,e,f,g:out std_logic);
end show;
ARCHITECTURE s of show is
  
 begin
  
  process(di)
   type data_out is array(0 to 6) of std_logic;
   variable output:data_out;
   begin
     case di is
     when 0=>output:="1111110";
     when 1=>output:="0110000";
     when 2=>output:="1101101";
     when 3=>output:="1111001";
     when 4=>output:="0110011";
     when 5=>output:="1011011";
     when 6=>output:="0011111";
     when 7=>output:="1110000";
     when 8=>output:="1111111";
     when 9=>output:="1110011";
     when others =>null;
     end case;
     a<=output(0);
     b<=output(1);
     c<=output(2);
     d<=output(3);
     e<=output(4);
     f<=output(5);
     g<=output(6);
     
  end process;
  end s;