/***************************************************************/
//MODULE:???
/******************************************************************/
//DEFINES
`define DEL 0   //????????
`define CNT_SZ 4 //?????????????PLL?????
`define DUTY 2   //DUTY???????????
                  //2?50?
//????
module PLL(reset,limit,clk, clk_in, reg_in1,clk_out);
//????
input reset; //PLL?????
input [`CNT_SZ-1:0] limit;//??????????4??????15
input clk;//??????
input clk_in;//????
output clk_out;//????
output reg_in1;

//????
wire reset;
wire [`CNT_SZ-1:0] limit;
wire clk;
wire clk_in;
wire clk_out;

reg [`CNT_SZ-1:0] counter;// ??????????
reg reg_in1;//???????
reg reg_in;


//??
assign #DEL clk_out =(counter>(limit/`DUTY))?1'b1:1'b0;


always@(posedge clk)
begin//4
           if(reset)  begin counter<=#DEL limit;end
           else  
           begin //5
                     reg_in<=clk_in;
	             reg_in1<=reg_in;    
                    if(((!reg_in1)&&clk_in))
                       begin
                         counter<=limit-1;
                       end//1
                   else
                     begin
              
                       if(counter==0)
                         counter<=limit;
                        else
                         counter<=counter-1;   
                     end   
             end//5       
               
end//4
endmodule