/***************************************************************/
//MODULE:dll
/******************************************************************/
`timescale 1ns/1ns
module test_dll;

reg reset; 
reg [3:0] limit;
reg clk;
reg clk_in;
wire clk_out;
wire reg_in1;
integer i;


always #5 clk=~clk;

initial
begin
   clk=1;reset=1;limit=5;clk_in=0;
    #40 reset=0;clk_in=1;
    for(i=0;i<10;i=i+1)
    begin 
    #60 clk_in=0;
    #120 clk_in=1;
    #240 clk_in=0;
    #60clk_in=1;
    #60 clk_in=0;
    end
    #10 $stop;
    


end
PLL  pll(reset,limit,clk, clk_in, reg_in1,clk_out);

endmodule