?? select7.rpt
字號:
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\select7\select7.rpt
select7
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - A -- OUTPUT 0 1 0 0 p
72 - - A -- OUTPUT 0 1 0 0 s
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\select7\select7.rpt
select7
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 23 OR2 1 3 0 2 |LPM_ADD_SUB:351|addcore:adder|:60
- 1 - A 21 OR2 3 0 0 2 :211
- 2 - A 21 OR2 ! 3 0 0 3 :217
- 4 - A 23 OR2 2 2 0 2 :285
- 2 - A 23 OR2 2 2 0 2 :291
- 1 - A 23 OR2 2 1 0 2 :297
- 5 - A 23 OR2 1 3 0 2 :325
- 8 - A 23 OR2 s 1 2 1 0 ~365~1
- 3 - A 23 OR2 1 2 1 0 :365
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\select7\select7.rpt
select7
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 4/ 48( 8%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\select7\select7.rpt
select7
** EQUATIONS **
m0 : INPUT;
m1 : INPUT;
m2 : INPUT;
m3 : INPUT;
m4 : INPUT;
m5 : INPUT;
m6 : INPUT;
-- Node name is 'p'
-- Equation name is 'p', type is output
p = _LC8_A23;
-- Node name is 's'
-- Equation name is 's', type is output
s = !_LC3_A23;
-- Node name is '|LPM_ADD_SUB:351|addcore:adder|:60' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = LCELL( _EQ001);
_EQ001 = !_LC1_A23 & _LC4_A23 & !m5
# !_LC2_A23 & _LC4_A23
# _LC2_A23 & !_LC4_A23 & m5
# _LC1_A23 & _LC2_A23 & !_LC4_A23;
-- Node name is ':211'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ002);
_EQ002 = m0 & m2
# m1 & m2
# m0 & m1;
-- Node name is ':217'
-- Equation name is '_LC2_A21', type is buried
!_LC2_A21 = _LC2_A21~NOT;
_LC2_A21~NOT = LCELL( _EQ003);
_EQ003 = m0 & m1 & !m2
# !m0 & !m1 & !m2
# m0 & !m1 & m2
# !m0 & m1 & m2;
-- Node name is ':285'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = LCELL( _EQ004);
_EQ004 = _LC1_A21 & _LC2_A21 & m3
# _LC1_A21 & m3 & m4
# _LC1_A21 & _LC2_A21 & m4;
-- Node name is ':291'
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = LCELL( _EQ005);
_EQ005 = _LC1_A21 & !_LC2_A21 & !m4
# _LC1_A21 & !m3 & !m4
# !_LC1_A21 & _LC2_A21 & m3
# _LC1_A21 & !_LC2_A21 & !m3
# !_LC1_A21 & m3 & m4
# !_LC1_A21 & _LC2_A21 & m4;
-- Node name is ':297'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ006);
_EQ006 = !_LC2_A21 & m3 & !m4
# _LC2_A21 & !m3 & !m4
# !_LC2_A21 & !m3 & m4
# _LC2_A21 & m3 & m4;
-- Node name is ':325'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = LCELL( _EQ007);
_EQ007 = _LC1_A23 & _LC2_A23 & !_LC4_A23 & m5
# !_LC2_A23 & _LC4_A23
# !_LC1_A23 & _LC4_A23
# _LC4_A23 & !m5;
-- Node name is '~365~1'
-- Equation name is '~365~1', location is LC8_A23, type is buried.
-- synthesized logic cell
_LC8_A23 = LCELL( _EQ008);
_EQ008 = _LC5_A23 & !m6
# _LC6_A23 & m6;
-- Node name is ':365'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = LCELL( _EQ009);
_EQ009 = _LC5_A23 & !m6
# _LC6_A23 & m6;
Project Information c:\select7\select7.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,032K
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