// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// Generated by Quartus II Version 4.0 (Build Build 184 12/18/2003)
// Created on Mon Jan 05 13:42:39 2004

//  Module Declaration
module state_m
( 
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	clk, reset, newt, sel, next, first
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
	// Port Declaration
	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk, reset, newt;
	output next, first;
	output [1:0]sel;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

	// Wire Declaration
	reg next, first;
	reg [1:0] sel;
	reg [2:0] filter;

parameter idle = 0, tap1 = 1, tap2 = 2, tap3 = 3, tap4 = 4;

always
begin
	case (filter)
		idle: begin
				sel = 0;
				next = 0;
				first = 0;
			  end

		tap1: begin
				sel = 0;
				next=0;
				first = 1;
			  end

		tap2: begin
				sel = 1;
				next=0;
				first = 0;
			  end

		tap3: begin
				sel = 2;
				next=0;
				first=0;
			  end

		tap4: begin
				sel = 3;
				next = 1;
				first=0;
			   end
			
		default : begin
					sel = 0;
					next = 0;
					first = 0;
					end
	endcase
end


always @(posedge clk or posedge reset)
begin
	if (reset)
		filter = idle;
	else
		case (filter)
			idle: begin
				if (newt)
					filter = tap1;
				  end
				
			tap1: begin
					filter = tap2;
				  end

			tap2: begin
					filter = tap3;
				  end

			tap3: begin
					filter = tap4;
				  end

			tap4: begin
					if (newt)
						filter = tap1;
					else
						filter = idle;
				   end
		endcase	

end		
endmodule