// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// Generated by Quartus II Version 4.0 (Build Build 184 12/18/2003)
// Created on Mon Jan 05 13:42:39 2004

//  Module Declaration
module acc
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	xh, clk, first, yn
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [10:0] xh;
	input clk;
	input first;
	output [7:0] yn;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

    reg [7:0]yn;
reg [11:0] ynm, inter, result, a_in;

// Describe Multiplexer

always @(first or result)
begin
	case (first)
		1'b 0: ynm = result;
		1'b 1: ynm = 12'b000000000000;
	endcase
end
	
always @(posedge clk)
begin
	result = inter;
end

always @(xh)
begin
	a_in[10:0] = (xh);
	a_in[11] = 0;
end

always @(result)
	begin 
		yn[7:0] = result[11:4];
	end

accum inst_1(.dataa(a_in), .datab(ynm), .result(inter));

endmodule