//
// Module: 	SelectRAM_A1
//
// Description: Verilog instantiation template
//		Block SelectRAM
//		Single Port 16,384 x 1 bit
//
// Device: 	VIRTEX-II Family 
//-------------------------------------------------------------------------------------------
//
// Syntax for Synopsys FPGA Express
// synopsys translate_off

  defparam  

//"Read during Write" attribute for functional simulation
	U_RAMB16_S1.WRITE_MODE = "READ_FIRST" -type string; //WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE 

//RAM initialization ("0" by default) for functional simulation: see example

// synopsys translate_on	


//Block SelectRAM Instantiation
RAMB16_S1 U_RAMB16_S1   (   .DI(),    //insert 1-bit data_in 
			    .ADDR(),  //insert 14-bit address bus ([13:0])
			    .EN(),    //insert enable signal
		 	    .WE(),    //insert write enable signal
			    .SSR(),   //insert set/reset signal
			    .CLK(),   //insert clock signal
			    .DO()     //insert 1-bit data_out 
			     );

// Attribute Decalrations:
  /* synopsys attribute 

Attribute "Read during Write mode" = WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE

	WRITE_MODE "READ_FIRST"
	*/
//Attributes for RAM initialization ("0" by default): see example