//
// Module:      BUFG_PHASE_CLKDV_SUBM
//
// Description: Verilog Submodule
//  DCM with CLKDV and CLK0 deskew with the fine phase adjustment feature in
//    VARIABLE mode. 
//  
// Device:  VIRTEX-II Family 
//
//---------------------------------------------------------------------

module BUFG_PHASE_CLKDV_SUBM (
                              CLK_IN,
                              RST,
                              PSEN,
                              PSINCDEC,
                              CLK_DIV,
                              CLK1X,
                              LOCK,
                              PSDONE
                             );

    input CLK_IN;
    input RST;
    input PSEN;
    input PSINCDEC;

    output CLK_DIV;
    output CLK1X;
    output LOCK;
    output PSDONE;

    wire CLK0_W;
    wire CLKDV_W;
    wire GND;

    assign GND = 1'b0;

    // BUFG Instantiation for CLK0//
    BUFG U0_BUFG (  
                  .I(CLK0_W),
                  .O(CLK1X)
                 );

    // BUFG Instantiation for CLK_DV//
    BUFG U1_BUFG (  
                  .I(CLKDV_W),
                  .O(CLK_DIV)
                 );
    
    // Attributes for functional simulation//
    // synopsys translate_off
       defparam U_DCM.CLKDV_DIVIDE = 4.0;      
       defparam U_DCM.DLL_FREQUENCY_MODE = "HIGH";
       defparam U_DCM.CLKOUT_PHASE_SHIFT = "VARIABLE";
       defparam U_DCM.PHASE_SHIFT = 0;
       defparam U_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
       defparam U_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
    // DCM Instantiation for the VARIABLE mode.
       DCM U_DCM ( 
                  .CLKFB(CLK1X), 
                  .CLKIN(CLK_IN), 
                  .DSSEN(GND), 
                  .PSCLK(CLK_IN), 
                  .PSEN(PSEN), 
                  .PSINCDEC(PSINCDEC), 
                  .RST(RST), 
                  .CLK0(CLK0_W), 
                  .CLKDV(CLKDV_W), 
                  .LOCKED(LOCK), 
                  .PSDONE(PSDONE)
                 );

    /* DCM Instantiation for the FIXED mode.Note that the PSCLK,PSEN,PSINCDEC signals
    are tied to Ground. The PSEN,PSINCDEC,PSDONE signals have to be removed from the
    module declaration and port list.
    DCM U_DCM ( 
               .CLKFB(CLK1X), 
               .CLKIN(CLK_IN), 
               .DSSEN(GND), 
               .PSCLK(GND), 
               .PSEN(GND), 
               .PSINCDEC(GND), 
               .RST(RST), 
               .CLK0(CLK0_W), 
               .CLKDV(CLKDV_W), 
               .LOCKED(LOCK)
              ); */


    // synthesis attribute declarations
     /* synopsys attribute
 
     CLKDV_DIVIDE "4.0"
     DLL_FREQUENCY_MODE "HIGH"
     CLKOUT_PHASE_SHIFT "VARIABLE"
     PHASE_SHIFT "0"
     DUTY_CYCLE_CORRECTION "TRUE"
     STARTUP_WAIT "FALSE"
     */
endmodule