//
// Module:      BUFG_DFS_FB_SUBM
//
// Description: Verilog Submodule
//  DCM with CLKFX and CLKFX180 outputs in phase with CLK_IN
//  
// Device:  VIRTEX-II Family 
//
//---------------------------------------------------------------------

module BUFG_DFS_FB_SUBM ( 
                         CLK_IN,
                         RST,
                         CLK1X,
                         CLKFX,
                         CLKFX180,
                         LOCK
                        );

    input CLK_IN;
    input RST;

    output CLK1X;
    output CLKFX;
    output CLKFX180;
    output LOCK;

    wire CLKFX_W;
    wire CLKFX180_W;
    wire CLK1X_W;
    wire GND;

    assign GND = 1'b0;

    // BUFG Instantiation for CLK1X//
    BUFG U0_BUFG (  
                  .I(CLK1X_W),
                  .O(CLK1X)
                 );

    // BUFG Instantiation for CLKFX//
    BUFG U1_BUFG (  
                  .I(CLKFX_W),
                  .O(CLKFX)
                 );

    // BUFG Instantiation for CLKFX180//
    BUFG U2_BUFG (  
                  .I(CLKFX180_W),
                  .O(CLKFX180)
                 );
   
    // Attributes for functional simulation//
    // synopsys translate_off
       defparam U_DCM.DFS_FREQUENCY_MODE = "LOW";
       defparam U_DCM.CLKFX_DIVIDE = 1;
       defparam U_DCM.CLKFX_MULTIPLY = 4;
       defparam U_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
     DCM U_DCM ( 
                .CLKIN(CLK_IN), 
                .CLKFB(CLK1X), 
                .DSSEN(GND), 
                .PSCLK(GND), 
                .PSEN(GND), 
                .PSINCDEC(GND), 
                .RST(RST), 
                .CLK0(CLK1X_W), 
                .CLKFX(CLKFX_W), 
                .CLKFX180(CLKFX180_W), 
                .LOCKED(LOCK)
               ); 
     
               
    // synthesis attribute declarations
     /* synopsys attribute
 
     DFS_FREQUENCY_MODE "LOW"
     CLKFX_DIVIDE "1"
     CLKFX_MULTIPLY "4"
     STARTUP_WAIT "FALSE"
     */
endmodule