//
// Module:      BUFG_CLKDV_SUBM
//
// Description: Verilog Submodule
//  DCM with CLKDV and CLK0 deskew
//  
// Device:  VIRTEX-II Family 
//
//---------------------------------------------------------------------

module BUFG_CLKDV_SUBM ( 
                        CLK_IN,
                        RST,
                        CLK1X,
                        CLK_DIV,
                        LOCK
                       );
    input CLK_IN;
    input RST;

    output CLK_DIV;
    output CLK1X;
    output LOCK;

    wire CLK0_W;
    wire CLKDV_W;
    wire GND;

    assign GND = 1'b0;

    // BUFG Instantiation for CLK0//
    BUFG U0_BUFG ( 
                  .I(CLK0_W),
                  .O(CLK1X)
                 );

    // BUFG Instantiation for CLKDV//
    BUFG U1_BUFG ( 
                  .I(CLKDV_W),
                  .O(CLK_DIV)
                 );
   
    // Attributes for functional simulation//
    // synopsys translate_off
       defparam U_DCM.CLKDV_DIVIDE = 4.0;     
       defparam U_DCM.DLL_FREQUENCY_MODE = "LOW";
       defparam U_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
       defparam U_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
    DCM U_DCM ( 
               .CLKFB(CLK1X), 
               .CLKIN(CLK_IN), 
               .DSSEN(GND), 
               .PSCLK(GND), 
               .PSEN(GND), 
               .PSINCDEC(GND), 
               .RST(RST), 
               .CLK0(CLK0_W), 
               .CLKDV(CLKDV_W), 
               .LOCKED(LOCK)
              );

    // synthesis attribute declarations
    /* synopsys attribute
 
    CLKDV_DIVIDE "4.0"
    DLL_FREQUENCY_MODE "LOW"
    DUTY_CYCLE_CORRECTION "TRUE"
    STARTUP_WAIT "FALSE"
   */
endmodule