//
// Module:      BUFG_CLK0_SUBM
//
// Description: Verilog Submodule
//		DCM with CLK0 deskew
//		
// Device: 	VIRTEX-II Family 
//
//---------------------------------------------------------------------

module BUFG_CKL0_SUBM (
                       CLK_IN,
                       RST,
                       CLK1X,
                       LOCK
                      );

    input CLK_IN;
    input RST;

    output CLK1X;
    output LOCK;
    
    wire CLK0_W;
    wire GND;

    assign GND = 1'b0;

    //BUFG Instantiation
    BUFG  U_BUFG (  
                  .I(CLK0_W),  
                  .O(CLK1X)
                 );
	 
    // Attributes for functional simulation//
    // synopsys translate_off
       defparam U_DCM.DLL_FREQUENCY_MODE = "LOW";
       defparam U_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
       defparam U_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
	 DCM U_DCM ( 
               .CLKFB(CLK1X), 
               .CLKIN(CLK_IN), 
               .DSSEN(GND), 
               .PSCLK(GND), 
               .PSEN(GND), 
               .PSINCDEC(GND), 
               .RST(RST), 
               .CLK0(CLK0_W),  
               .LOCKED(LOCK)
              );

    // synthesis attribute declarations
      /* synopsys attribute 

	   DLL_FREQUENCY_MODE "LOW"
	   DUTY_CYCLE_CORRECTION "TRUE"
	   STARTUP_WAIT "FALSE"
      */
endmodule