//
// Module:      BUFG_CLK0_FB_SUBM
//
// Description: Verilog Submodule
//		DCM with CLK0 internal and external (board level) deskew. 
//		
// Device: 	VIRTEX-II Family 
//
//---------------------------------------------------------------------

module BUFG_CLK0_FB_SUBM ( 
                          CLK_IN,
                          RST,
                          CLKFB,
                          CLK1X_EXT,
                          CLK1X_INT,
                          LOCK_INT,
                          LOCK_EXT
                         );

    input CLK_IN;
    input RST;
    input CLKFB;

    output CLK1X_EXT;
    output CLK1X_INT;
    output LOCK_INT;
    output LOCK_EXT;

    wire CLK_IN_W;
    wire CLKFB_W;
    wire CLK0_INT_W;
    wire GND;       

    assign GND = 1'b0;

    // IBUFG Instantiation for CLK_IN//
    IBUFG U_IBUFG0 ( 
                    .I(CLK_IN),
                    .O(CLK_IN_W)
                   );

    // IBUFG Instantiation for CLKFB//
    IBUFG U_IBUFG1 (
                    .I(CLKFB),
                    .O(CLKFB_W) 
                   );

    // BUFG Instantiation for internal clock distribution//
    BUFG U_BUFG ( 
                 .I(CLK0_INT_W),
                 .O(CLK1X_INT) 
                );
 
	 	 
    // Attributes for functional simulation//
    // synopsys translate_off
       defparam U0_DCM.DLL_FREQUENCY_MODE = "LOW";
       defparam U0_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
       defparam U0_DCM.STARTUP_WAIT = "FALSE";
       defparam U1_DCM.DLL_FREQUENCY_MODE = "LOW";
       defparam U1_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
       defparam U1_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
    DCM U0_DCM ( 
                .CLKFB(CLKFB_W), 
                .CLKIN(CLK_IN_W), 
                .DSSEN(GND), 
                .PSCLK(GND), 
                .PSEN(GND), 
                .PSINCDEC(GND), 
                .RST(RST), 
                .CLK0(CLK1X_EXT), 
                .LOCKED(LOCK_EXT)
               );

     DCM U1_DCM ( 
                 .CLKFB(CLK1X_INT), 
                 .CLKIN(CLK_IN_W), 
                 .DSSEN(GND), 
                 .PSCLK(GND), 
		 .PSEN(GND), 
                 .PSINCDEC(GND), 
                 .RST(RST), 
                 .CLK0(CLK0_INT_W), 
                 .LOCKED(LOCK_INT)
                );

     // synthesis attribute declarations
     /* synopsys attribute 
 	  DLL_FREQUENCY_MODE "LOW"
	  DUTY_CYCLE_CORRECTION "TRUE"
	  STARTUP_WAIT "FALSE"
     */
endmodule