//
// Module: 	DDR_Output
//
// Description: Verilog instantiation template
//		Double Data Rate Output
//		
//
// Device: 	VIRTEX-II Family 
//--------------------------------------------------------------------------

module DDR_Output (d0 , d1, q, clk, clk180, rst, set, ce);

input d0, d1, clk, clk180, rst, set, ce;
output q;


//Synchronous Output DDR primitive instantiation

FDDRRSE U1  (.D0(d0),
	     .D1(d1),
	     .C0(clk),
	     .C1(clk180),
	     .CE(ce),
	     .R(rst),
	     .S(set),
	     .Q(q)
	    );
endmodule