//
// Module: 	XC2V_RAM64XN_S
//
// Description: Distributed SelectRAM example
//		Single Port 64 x N-bit
//		Use template "SelectRAM_64S.v"
//		and registered outputs (optional)
//
// Device: 	VIRTEX-II Family
//---------------------------------------------------------------------------------------

module XC2V_RAM64XN_S (DATA_IN, ADDRESS, WRITE_EN, CLK, O_DATA_OUT);

parameter data_width = 8;//Replace with desired data-bus width 
                         
input [data_width-1:0]DATA_IN;
input [5:0] ADDRESS;
input WRITE_EN;
input CLK;

output [data_width-1:0]O_DATA_OUT;
reg [data_width-1:0]O_DATA_OUT;

wire [data_width-1:0]DATA_OUT;


/*Remember to Instantiate a Distributed SelectRam block for each Data port
  and to give each instance a unique name...The following is an example of instantiation 
  for a 64 X 8-bit RAM. */

//Distributed SelectRAM Instantiation - Data-Port 0	
 
   RAM64X1S U_RAM64X1S_0(  .D(DATA_IN[0]),    //insert input signal
       			   .WE(WRITE_EN),     //insert Write Enable signal
			   .WCLK(CLK),        //insert Write Clock signal
			   .A0(ADDRESS[0]),   //insert Address 0 signal
			   .A1(ADDRESS[1]),   //insert Address 1 signal
			   .A2(ADDRESS[2]),   //insert Address 2 signal
			   .A3(ADDRESS[3]),   //insert Address 3 signal
			   .A4(ADDRESS[4]),   //insert Address 4 signal
			   .A5(ADDRESS[5]),   //insert Address 5 signal
			   .O(DATA_OUT[0])    //insert output signal
		         );

//Distributed SelectRAM Instantiation - Data-Port 1		
 
   RAM64X1S U_RAM64X1S_1(  .D(DATA_IN[1]),    //insert input signal
       			   .WE(WRITE_EN),     //insert Write Enable signal
			   .WCLK(CLK),   //insert Write Clock signal
			   .A0(ADDRESS[0]),   //insert Address 0 signal
			   .A1(ADDRESS[1]),   //insert Address 1 signal
			   .A2(ADDRESS[2]),   //insert Address 2 signal
			   .A3(ADDRESS[3]),   //insert Address 3 signal
			   .A4(ADDRESS[4]),   //insert Address 4 signal
 			   .A5(ADDRESS[5]),   //insert Address 5 signal
			   .O(DATA_OUT[1])    //insert output signal
		         );

//Distributed SelectRAM Instantiation - Data-Port 2		
 
   RAM64X1S U_RAM64X1S_2(  .D(DATA_IN[2]),    //insert input signal
       			   .WE(WRITE_EN),     //insert Write Enable signal
			   .WCLK(CLK),   //insert Write Clock signal
			   .A0(ADDRESS[0]),   //insert Address 0 signal
			   .A1(ADDRESS[1]),   //insert Address 1 signal
			   .A2(ADDRESS[2]),   //insert Address 2 signal
			   .A3(ADDRESS[3]),   //insert Address 3 signal
			   .A4(ADDRESS[4]),   //insert Address 4 signal
			   .A5(ADDRESS[5]),   //insert Address 5 signal
			   .O(DATA_OUT[2])    //insert output signal
		         );

//Distributed SelectRAM Instantiation - Data-Port 3		
 
   RAM64X1S U_RAM64X1S_3(  .D(DATA_IN[3]),    //insert input signal
       			   .WE(WRITE_EN),     //insert Write Enable signal
			   .WCLK(CLK),   //insert Write Clock signal
			   .A0(ADDRESS[0]),   //insert Address 0 signal
			   .A1(ADDRESS[1]),   //insert Address 1 signal
			   .A2(ADDRESS[2]),   //insert Address 2 signal
			   .A3(ADDRESS[3]),   //insert Address 3 signal
			   .A4(ADDRESS[4]),   //insert Address 4 signal
			   .A5(ADDRESS[5]),   //insert Address 5 signal
			   .O(DATA_OUT[3])    //insert output signal
		         );
 	

//Distributed SelectRAM Instantiation - Data-Port 4		
 
   RAM64X1S U_RAM64X1S_4(  .D(DATA_IN[4]),    //insert input signal
       			   .WE(WRITE_EN),     //insert Write Enable signal
			   .WCLK(CLK),   //insert Write Clock signal
			   .A0(ADDRESS[0]),   //insert Address 0 signal
			   .A1(ADDRESS[1]),   //insert Address 1 signal
			   .A2(ADDRESS[2]),   //insert Address 2 signal
			   .A3(ADDRESS[3]),   //insert Address 3 signal
			   .A4(ADDRESS[4]),   //insert Address 4 signal
			   .A5(ADDRESS[5]),   //insert Address 5 signal
			   .O(DATA_OUT[4])    //insert output signal
		         );

//Distributed SelectRAM Instantiation - Data-Port 5		
 
   RAM64X1S U_RAM64X1S_5(  .D(DATA_IN[5]),    //insert input signal
       			   .WE(WRITE_EN),     //insert Write Enable signal
			   .WCLK(CLK),   //insert Write Clock signal
			   .A0(ADDRESS[0]),   //insert Address 0 signal
			   .A1(ADDRESS[1]),   //insert Address 1 signal
			   .A2(ADDRESS[2]),   //insert Address 2 signal
			   .A3(ADDRESS[3]),   //insert Address 3 signal
			   .A4(ADDRESS[4]),   //insert Address 4 signal
			   .A5(ADDRESS[5]),   //insert Address 5 signal
			   .O(DATA_OUT[5])    //insert output signal
		         );

//Distributed SelectRAM Instantiation - Data-Port 6		
 
   RAM64X1S U_RAM64X1S_6(  .D(DATA_IN[6]),    //insert input signal
       			   .WE(WRITE_EN),     //insert Write Enable signal
			   .WCLK(CLK),   //insert Write Clock signal
			   .A0(ADDRESS[0]),   //insert Address 0 signal
			   .A1(ADDRESS[1]),   //insert Address 1 signal
			   .A2(ADDRESS[2]),   //insert Address 2 signal
			   .A3(ADDRESS[3]),   //insert Address 3 signal
			   .A4(ADDRESS[4]),   //insert Address 4 signal
			   .A5(ADDRESS[5]),   //insert Address 5 signal
			   .O(DATA_OUT[6])    //insert output signal
		         );

//Distributed SelectRAM Instantiation - Data-Port 7	
 
   RAM64X1S U_RAM64X1S_7(  .D(DATA_IN[7]),    //insert input signal
       			   .WE(WRITE_EN),     //insert Write Enable signal
			   .WCLK(CLK),   //insert Write Clock signal
			   .A0(ADDRESS[0]),   //insert Address 0 signal
			   .A1(ADDRESS[1]),   //insert Address 1 signal
			   .A2(ADDRESS[2]),   //insert Address 2 signal
			   .A3(ADDRESS[3]),   //insert Address 3 signal
			   .A4(ADDRESS[4]),   //insert Address 4 signal
			   .A5(ADDRESS[5]),   //insert Address 5 signal
			   .O(DATA_OUT[7])    //insert output signal
		         );


//Registered outputs / Synchronous read
always @(posedge CLK)

  O_DATA_OUT <= DATA_OUT;


endmodule