?? ddr_lvds_3state.v
字號:
//
// Module: DDR_LVDS_3STATE
//
// Description: Verilog Instantiation Template
// DDR 3-State Flip-Flops with LVDS 3-State output buffer
//
//
// Device: VIRTEX-II Family
//
//---------------------------------------------------------------------
//
//Synchronous Output DDR primitive instantiation
FDDRRSE U1 ( .D0(), //1st Bit Data-In
.D1(), //2nd Bit Data-In
.C0(), //Clock input for 1st bit
.C1(), //Clock input for 2nd bit (180 deg. output from DLL or ~C0)
.CE(), //Clock Enable
.R(), //Reset
.S(), //Set
.Q() //DDR data out
);
//Synchronous 3-State DDR primitive instantiation
FDDRRSE U2 ( .D0(), //1st Bit 3-State In
.D1(), //2nd Bit 3-State In
.C0(), //Clock input for 1st bit
.C1(), //Clock input for 2nd bit (180 deg. output from DLL or ~C0)
.CE(), //Clock Enable
.R(), //Reset
.S(), //Set
.Q() //DDR 3-State out
);
//3-State LVDS buffer instantiation
OBUFTDS_LVDS_25 U3 ( .I(), // Input to LVDS buffer = DDR data out
.T(), // 3-State input to LVDS buffer = DDR 3-State out
.O(), // P-Channel Output of LVDS buffer
.OB() // N-Channel Output of LVDS buffer
);
//---------------------------------------------------------------------
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