?? unsigned_mult_8x8_rr.v
字號:
//// Module: UNSIGNED_MULT_8X8//// Description: Verilog Sub-module// 8-bit X 8-bit embedded unsigned multiplier (asynchronous)//// Device: Virtex-II Family//// Copyright (c) 2000 Xilinx, Inc. All rights reserved.////////////////////////////////////////////////////////////////////////////////////////module UNSIGNED_MULT_8X8 (A, B, P, CLK, RESET);input CLK;input RESET;input [7:0] A;input [7:0] B;output [15:0] P;wire [15:0] P;reg [7:0] ar, br;reg [15:0] pr;wire [15:0] p_async;always @ (posedge CLK or posedge RESET)if (RESET) begin ar <= 8'h0; br <= 8'h0; pr <= 16'h0; endelse begin ar <= A; br <= B; pr <= p_async; endassign P = pr;//// Instantiation Section//MULT8X8_U DUT ( .A (ar) , // insert input signal #1 .B (br) , // insert input signal #2 .P (p_async) // insert output signal );//////////////////////////////////////////////////////////////////////////////////////endmodule
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