//// Module: UNSIGNED_MULT_4X4//// Description: Verilog Sub-module// 4-bit X 4-bit embedded unsigned multiplier (asynchronous)//// Device: Virtex-II Family//// Copyright (c) 2000 Xilinx, Inc.  All rights reserved.////////////////////////////////////////////////////////////////////////////////////////module UNSIGNED_MULT_4X4 (A, B, P, CLK, RESET);input CLK;input RESET;input [3:0] A;input [3:0] B;output [7:0] P;wire [7:0] P;reg [3:0] ar, br;reg [7:0] pr;wire [7:0] p_async;always @ (posedge CLK or posedge RESET)if (RESET)  begin    ar <= 4'h0;    br <= 4'h0;    pr <= 8'h0;  endelse  begin    ar <= A;    br <= B;    pr <= p_async;  endassign P = pr;//// Instantiation Section//MULT4X4_U DUT  ( .A (ar) , // insert input signal #1    .B (br) , // insert input signal #2    .P (p_async)   // insert output signal  );//////////////////////////////////////////////////////////////////////////////////////endmodule