//
// Module: 	SRLC128E
//
// Description: SelectShiftRegister-II macro
//		128 bit Shift Register with Carry and Clock Enable
//		Use template "SRLC16E.v"
//
// Device: 	VIRTEX-II Family
//
// Date:	SAK / 04-17-2000 - XILINX
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 2000 Xilinx, Inc.  All rights reserved.
//-----------------------------------------------------------------------------------------------------

module SRLC128E (D, CE, CLK, A0, A1, A2, A3, A4, A5, A6, Q, Q128);

input D;
input CLK;
input CE;
input A0, A1, A2, A3, A4, A5, A6;

output Q;
output Q128;

wire Q15;
wire Q31;
wire Q47;
wire Q63;
wire Q79;
wire Q95;
wire Q111;
wire Q_MUX_00_15;
wire Q_MUX_16_31;
wire Q_MUX_32_47;
wire Q_MUX_48_63;
wire Q_MUX_64_79;
wire Q_MUX_80_95;
wire Q_MUX_96_111;
wire Q_MUX_112_127;
wire F5_MUXOUT_00_31;
wire F5_MUXOUT_32_63;
wire F5_MUXOUT_64_95;
wire F5_MUXOUT_96_127;
wire F6_MUX_OUT_00_63;
wire F6_MUX_OUT_64_127;





//Instantiate 16-bit shift registers: SRLC16E//
   SRLC16E U_SRLC16E_0 ( .D(D),
			 .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_00_15),
                         .Q15(Q15)
		       );

   SRLC16E U_SRLC16E_1 ( .D(Q15),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_16_31),
                         .Q15(Q31) 
			);

   SRLC16E U_SRLC16E_2 ( .D(Q31),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_32_47),
                         .Q15(Q47) 
			);

   SRLC16E U_SRLC16E_3 ( .D(Q47),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_48_63),
                         .Q15(Q63) 
			);

   SRLC16E U_SRLC16E_4 ( .D(Q63),
			 .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_64_79),
                         .Q15(Q79)
		       );

   SRLC16E U_SRLC16E_5 ( .D(Q79),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_80_95),
                         .Q15(Q95) 
			);

   SRLC16E U_SRLC16E_6 ( .D(Q95),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_96_111),
                         .Q15(Q111) 
			);

   SRLC16E U_SRLC16E_7 ( .D(Q111),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_112_127),
                         .Q15(Q128) 
			);


//Instantiate MUXF5, F6, and F7 for Addressable output//
    MUXF5_L    U_MUX5_0( .LO(F5_MUXOUT_00_31),
                         .I0(Q_MUX_00_15),
                         .I1(Q_MUX_16_31),
                         .S(A4)
			);

    MUXF5_L    U_MUX5_1( .LO(F5_MUXOUT_32_63),
                         .I0(Q_MUX_32_47),
                         .I1(Q_MUX_48_63),
                         .S(A4)
			);

    MUXF5_L    U_MUX5_2( .LO(F5_MUXOUT_64_95),
                         .I0(Q_MUX_64_79),
                         .I1(Q_MUX_80_95),
                         .S(A4)
			);

    MUXF5_L    U_MUX5_3( .LO(F5_MUXOUT_96_127),
                         .I0(Q_MUX_96_111),
                         .I1(Q_MUX_112_127),
                         .S(A4)
			);
    

    MUXF6      U_MUX6_0( .O(F6_MUX_OUT_00_63),
                         .I0(F5_MUXOUT_00_31),
                         .I1(F5_MUXOUT_32_63),
                         .S(A5)
			);

    MUXF6      U_MUX6_1( .O(F6_MUX_OUT_64_127),
                         .I0(F5_MUXOUT_64_95),
                         .I1(F5_MUXOUT_96_127),
                         .S(A5)
			);

    MUXF7      U_MUX7  ( .O(Q),
                         .I0(F6_MUX_OUT_00_63),
                         .I1(F6_MUX_OUT_64_127),
                         .S(A6)
			);

endmodule