README file: Virtex-II Platform FPGA Handbook
=============================================

Date: March, 2001

Verilog code examples are provided to illustrate the Chapter 2 - Design Considerations - of 
the Virtex-II Platform FPFA Handbook.

- Verilog Templates:
Verilog templates are available as examples to instantiate primitives. 

- Verilog Submodules:
Verilog submodules are low level Verilog code instantiating some primitives. 
These submodules can be instantiated in a design and must be synthesized with the design.

The templates and submodules can be found in the following directories corresponding to 
each section of the Chapter 2: Design Considerations (Virtex-II Platform FPGA HandBook)

Directory:
------------

- shift_registers: "Using Shift Register Look-up Tables"

Templates (primitive):
 SRL16E.v

Submodules (code example):
 SRLC16E.v
 SRLC32E.v
 SRLC64E.v
 SRL128E.v
 SRLC32E_MACRO.v
 SRLC64E_MACRO.v
 SRLC128E_MACRO.v
 

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