-- MAX+plus II Compiler Fit File      
-- Version 10.0 9/14/2000             
-- Compiled: 01/04/2005 13:52:06      

-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "cnt99"
BEGIN

    DEVICE = "EPM7032VLC44-12";

    "clk2"                         : INPUT_PIN  = 43     ;
    "d0"                           : INPUT_PIN  = 11     ; -- LC7
    "d1"                           : INPUT_PIN  = 9      ; -- LC6
    "d2"                           : INPUT_PIN  = 8      ; -- LC5
    "d3"                           : INPUT_PIN  = 7      ; -- LC4
    "load2"                        : INPUT_PIN  = 5      ; -- LC2
    "reset2"                       : INPUT_PIN  = 4      ; -- LC1
    "updownp"                      : INPUT_PIN  = 6      ; -- LC3
    "coutp"                        : OUTPUT_PIN = 32     ; -- LC25
    "enable"                       : OUTPUT_PIN = 29     ; -- LC27
    "ss"                           : OUTPUT_PIN = 31     ; -- LC26
    "y00"                          : OUTPUT_PIN = 33     ; -- LC24
    "y01"                          : OUTPUT_PIN = 36     ; -- LC22
    "y02"                          : OUTPUT_PIN = 37     ; -- LC21
    "y03"                          : OUTPUT_PIN = 39     ; -- LC19
    "y10"                          : OUTPUT_PIN = 41     ; -- LC17
    "y11"                          : OUTPUT_PIN = 34     ; -- LC23
    "y12"                          : OUTPUT_PIN = 40     ; -- LC18
    "y13"                          : OUTPUT_PIN = 38     ; -- LC20
    "|LPM_ADD_SUB:196|addcore:adder|addcore:adder0|result_node2" : LOCATION   = LC29   ; -- PIN 27

END;

INTERNAL_INFO "cnt99"
BEGIN
	DEVICE = EPM7032VLC44-12;
	LC27    : LORAX = "G40R0";
	LC19    : LORAX = "G15R0,PA3R0C1";
	LC21    : LORAX = "G30R0,PA16R0C1";
	LC22    : LORAX = "G31R0,PA14R0C1";
	LC24    : LORAX = "G33R0,PA10R0C1";
	LC20    : LORAX = "G16R0,PA1R0C1";
	LC18    : LORAX = "G14R0,PA5R0C1";
	LC23    : LORAX = "G32R0,PA12R0C1";
	LC17    : LORAX = "G13R0,PA7R0C1";
	LC26    : LORAX = "G39R0";
	LC25    : LORAX = "G38R0";
	OH0R0P4 : LORAX = "G43R0,PA20R0C1";
	OH3R0P7 : LORAX = "G46R0,PA24R0C1";
	OH1R0P5 : LORAX = "G44R0,PA19R0C1";
	OH2R0P6 : LORAX = "G45R0,PA22R0C1";
	LC29    : LORAX = "G55R0,PA27R0C1";
	OH4R0P8 : LORAX = "G60R0,PA29R0C1";
	OH5R0P9 : LORAX = "G61R0,PA28R0C1";
	OH6R0P11 : LORAX = "G62R0,PA31R0C1";
END;