`include "inc.h"//*******************************************************************************//  S Y N T H E Z I A B L E      S D R A M     C O N T R O L L E R    C O R E////  This core adheres to the GNU Public License  // //  This is a synthesizable Synchronous DRAM controller Core.  As it stands,//  it is ready to work with 8Mbyte SDRAMs, organized as 2M x 32 at 100MHz//  and 125MHz. For example: Samsung KM432S2030CT,  Fujitsu MB81F643242B.////  The core has been carefully coded so as to be "platform-independent".  //  It has been successfully compiled and simulated under three separate//  FPGA/CPLD platforms://      Xilinx Foundation Base Express V2.1i//      Altera Max+PlusII V9.21//      Lattice ispExpert V7.0//  //  The interface to the host (i.e. microprocessor, DSP, etc) is synchronous//  and supports ony one transfer at a time.  That is, burst-mode transfers//  are not yet supported.  In may ways, the interface to this core is much//  like that of a typical SRAM.  The hand-shaking between the host and the //  SDRAM core is done through the "sdram_busy_l" signal generated by the //  core.  Whenever this signal is active low, the host must hold the address,//  data (if doing a write), size and the controls (cs, rd/wr).  ////  Connection Diagram://  SDRAM side://  sd_wr_l                     connect to -WR pin of SDRAM//  sd_cs_l                     connect to -CS pin of SDRAM//  sd_ras_l                    connect to -RAS pin of SDRAM//  sd_cas_l                    connect to -CAS pin of SDRAM//  sd_dqm[3:0]                 connect to the DQM3,DQM2,DQM1,DQM0 pins//  sd_addx[10:0]               connect to the Address bus [10:0]//  sd_data[31:0]               connect to the data bus [31:0]//  sd_ba[1:0]                  connect to BA1, BA0 pins of SDRAM//   //  HOST side://  mp_addx[22:0]               connect to the address bus of the host. //                              23 bit address bus give access to 8Mbyte//                              of the SDRAM, as byte, half-word (16bit)//                              or word (32bit)//  mp_data_in[31:0]            Unidirectional bus connected to the data out//                              of the host. To use this, enable //                              "databus_is_unidirectional" in INC.H//  mp_data_out[31:0]           Unidirectional bus connected to the data in //                              of the host.  To use this, enable//                              "databus_is_unidirectional" in INC.H//  mp_data[31:0]               Bi-directional bus connected to the host's//                              data bus.  To use the bi-directionla bus,//                              disable "databus_is_unidirectional" in INC.H//  mp_rd_l                     Connect to the -RD output of the host//  mp_wr_l                     Connect to the -WR output of the host//  mp_cs_l                     Connect to the -CS of the host//  mp_size[1:0]                Connect to the size output of the host//                              if there is one.  When set to 0//                              all trasnfers are 32 bits, when set to 1//                              all transfers are 8 bits, and when set to//                              2 all xfers are 16 bits.  If you want the//                              data to be lower order aligned, turn on//                              "align_data_bus" option in INC.H//  sdram_busy_l                Connect this to the wait or hold equivalent//                              input of the host.  The host, must hold the//                              bus if it samples this signal as low.//  sdram_mode_set_l            When a write occurs with this set low,//                              the SDRAM's mode set register will be programmed//                              with the data supplied on the data_bus[10:0].//////  Author:  Jeung Joon Lee  joon.lee@quantum.com,  cmosexod@ix.netcom.com//  //*******************************************************************************////  Hierarchy:////  SDRAM.V         Top Level Module//  HOSTCONT.V      Controls the interfacing between the micro and the SDRAM//  SDRAMCNT.V      This is the SDRAM controller.  All data passed to and from//                  is with the HOSTCONT.//  optional//  MICRO.V         This is the built in SDRAM tester.  This module generates //                  a number of test logics which is used to test the SDRAM//                  It is basically a Micro bus generator. //  /**/ module sdram(            // SYSTEM LEVEL CONNECTIONS            sys_rst_l,            sys_clk,            // SDRAM CONNECTIONS            sd_wr_l,            sd_cs_l,            sd_ras_l,            sd_cas_l,            sd_dqm,            sd_addx,            sd_data,            sd_ba,            // MICROPORCESSOR CONNECTION            mp_addx`ifdef databus_is_unidirectional            ,            mp_data_in,            mp_data_out,`else            ,            mp_data,`endif            mp_rd_l,            mp_wr_l,            mp_cs_l,            sdram_mode_set_l,            sdram_busy_l,            mp_size,            next_state                        // DEBUG`ifdef show_debug            ,                        next_state,            mp_data_out_sd,            mp_data_gate            do_write,            reg_mp_addx,            reg_mp_data_mux,            sd_addx_mux,            sd_addx10_mux,            next_state,            doing_refresh,            do_modeset,            do_read,            sd_addx_mux,            sd_addx10_mux,            autorefresh_cntr,            autorefresh_cntr_l,            pwrup,            top_state,            wr_cntr,            mp_data_micro,            mp_data_mux,            sd_data_ena,            mp_data_out,            sd_addx_mux,            sd_addx10_mux,            sd_rd_ena`endif );// ****************************************////   I/O  DEFINITION//// ****************************************// SYSTEM LEVEL CONNECTIONSinput           sys_clk;                // global system clock.  Runs the sdram state machineinput           sys_rst_l;              // global active low asynchronous system reset// SDRAM CONNECTIONSoutput          sd_wr_l;                // SDRAM active low WRITE signaloutput          sd_cs_l;                // SDRAM active low chip select signaloutput          sd_ras_l;               // SDRAM active low RAS output          sd_cas_l;               // SDRAM active low CASoutput  [3:0]   sd_dqm;                 // SDRAM data masksoutput  [10:0]  sd_addx;                // SDRAM multiplexed address businout   [31:0]  sd_data;                // SDRAM birectional data bus 32 bitoutput  [1:0]   sd_ba;                  // SDRAM bank address , aka A11// MICROPROCESSOR CONNECTION`ifdef databus_is_unidirectionalinput   [31:0]  mp_data_in;             output  [31:0]  mp_data_out;`else`ifdef simulate_mpinout   [31:0]  mp_data;`elseoutput      [31:0]  mp_data;`endif`endif`ifdef simulate_mpoutput  [22:0]  mp_addx;                // HOST address bus. 23 bits for 8Mboutput          mp_rd_l;                // HOST active low READ output          mp_wr_l;                // HOST active low WRITEoutput          mp_cs_l;                // HOST active low chip selectoutput          sdram_mode_set_l;output  [1:0]   mp_size;                // 00=32bits, 10=16bits, 01=8bits`elseinput   [22:0]  mp_addx;                // HOST address bus. 23 bits for 8Mbinput           mp_rd_l;                // HOST active low READ input           mp_wr_l;                // HOST active low WRITEinput           mp_cs_l;                // HOST active low chip selectinput           sdram_mode_set_l;input   [1:0]   mp_size;                // 00=32bits, 10=16bits, 01=8bits`endifoutput          sdram_busy_l;output  [3:0]   next_state;// DEBUG`ifdef show_debugoutput  [31:0]  mp_data_out_sd;output          mp_data_gate;output          do_write;output  [22:0]  reg_mp_addx;output  [31:0]  reg_mp_data_mux;output          sd_addx_mux;output          sd_addx10_mux;output          do_modeset;output          do_read;output          doing_refresh;output  [3:0]   next_state;output  [12:0]  autorefresh_cntr;output          autorefresh_cntr_l;output          pwrup;output  [3:0]   top_state;output  [7:0]   wr_cntr;//output[31:0]  mp_data_micro;output  [31:0]  mp_data_out;//output        mp_data_mux;output          sd_data_ena;output          sd_rd_ena;`endif// INTER-MODULE CONNECTIONSwire            do_modeset;wire            do_read;wire            do_write;wire            doing_refresh;wire            sd_addx_ena;wire    [1:0]   sd_addx_mux;wire    [1:0]   sd_addx10_mux;wire            sd_rd_ena;wire            sd_data_ena;wire    [2:0]   modereg_cas_latency;wire    [2:0]   modereg_burst_length;wire    [3:0]   next_state;wire    [31:0]  mp_data_out_sd;wire    [31:0]  mp_data_in;