//PCI ARBITER TEST FIXTURE

`timescale 1ns/1ns
`define halfperiod 15
`define period 30

module t();

reg[1:6] REQ_;
reg reset_,clk_in,frame_,irdy_;
wire [1:6]GNT_;
wire [31:0]adbus;
wire [3:0]cbe;
integer i;

Arbiter m(REQ_, reset_, clk_in, frame_, irdy_, GNT_, adbus, cbe);

initial
begin
clk_in = 0;
reset_ = 0;
REQ_ = 6'b111111;
frame_ = 1'b1;
end


//CLOCK GENERATION

always
begin
#`halfperiod clk_in = !clk_in;
end

initial
begin

#5 reset_ = 1'b1;
#5 frame_ = 1'b1;

//ROTATIONAL PRIORITY
#2       REQ_ = 6'b001111;
#`period REQ_ = 6'b100111;
#`period REQ_ = 6'b100111;
#`period REQ_ = 6'b100111;
#`period REQ_ = 6'b100111;
#`period REQ_ = 6'b100111;

end


//16 CLOCK LATENCY
initial
begin

#163 frame_ = 1'b1;
#164 REQ_ = 6'b001111;
#193 frame_ = 1'b0;
#223 frame_ = 1'b1;

end

endmodule