// HDLi Version 3.0 (beta)
// Parameters: compare -b 3 -eq     -S 0 -p 3   -l vsc983 -Synopsys -rtl -nentity -nadd_p -ntiming -verilog -br 0,4,8,12,32,0  
// spi_equal3: 9.00 physical gates (vsc983)
// spi_equal3: 233.37 squm area (vsc983)
// -----------------------------------------------------------------------------
//                            VLSI Technology, Inc.
// -----------------------------------------------------------------------------
// Copyright 1999 by VLSI Technology, Inc. All rights reserved.
// 
// This module is property of VLSI Technology, Inc (VLSI) and its use is
// granted to the customer for the sole purpose of implementing in silicon
// provided by VLSI. This module may only be used in accordance with the
// provisions of the Design Integrator License Agreement.
// 
// -----------------------------------------------------------------------------
//                        Comparator Compiler Version 1.0a
// -----------------------------------------------------------------------------
// spi_equal3 : structural Verilog
// "spi_equal3_rtl.v" contains the RTL Verilog
//
// Compiled by coste_e on Fri Jun 18 10:49:48 1999
// -----------------------------------------------------------------------------

module spi_equal3 (
                   a,
                   b,
                   aeqb);

   input  [2:0] a;
   input  [2:0] b;
   output       aeqb;

   supply1 vdd;
   supply0 vss;


   wire   n000003;
   assign n000003 = a[2];
   wire   n000002;
   assign n000002 = a[1];
   wire   n000001;
   assign n000001 = a[0];
   wire   n000006;
   assign n000006 = b[2];
   wire   n000005;
   assign n000005 = b[1];
   wire   n000004;
   assign n000004 = b[0];
   wire   n000007;
   assign aeqb = n000007;

   an03d1  u000001(
                   .a1(n000011),
                   .a2(n000012),
                   .a3(n000013),
                   .z(n000007));
   xn02d1  u000002(
                   .a1(n000003),
                   .a2(n000006),
                   .zn(n000013));
   xn02d1  u000003(
                   .a1(n000002),
                   .a2(n000005),
                   .zn(n000012));
   xn02d1  u000004(
                   .a1(n000001),
                   .a2(n000004),
                   .zn(n000011));

endmodule // spi_equal3

// -----------------------------------------------------------------------------
// Verilog Component Instantiation:
// -----------------------------------------------------------------------------
/*
   spi_equal3 u1 (.a(),        //  3 bit Source Operand
                  .b(),        //  3 bit Source Operand
                  .aeqb());    // A == B

*/
// -----------------------------------------------------------------------------
// Verilog Synthesis Commands:
// -----------------------------------------------------------------------------
/*
   set_dont_touch find(design, spi_equal3, -hierarchy)
   remove_attribute find(design, spi_equal3, -hierarchy) dont_touch
   set_ungroup find(design, spi_equal3, -hierarchy)
*/
// -----------------------------------------------------------------------------