Release 6.3i Par G.35Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.USER-MA::  Sat Apr 22 18:30:00 2006C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 dled_map.ncd dled.ncd
dled.pcf Constraints file: dled.pcfLoading device database for application Par from file "dled_map.ncd".   "dled" is an NCD, version 2.38, device xc2s100, package pq208, speed -5Loading device for application Par from file 'v100.nph' in environment
C:/Xilinx.Device speed data version:  PRODUCTION 1.27 2004-06-25.Resolved that GCLKIOB <clk> must be placed at site P77.Resolved that IOB <seg<0>> must be placed at site P34.Resolved that IOB <seg<1>> must be placed at site P31.Resolved that IOB <seg<2>> must be placed at site P41.Resolved that IOB <seg<3>> must be placed at site P36.Resolved that IOB <seg<4>> must be placed at site P35.Resolved that IOB <seg<5>> must be placed at site P33.Resolved that IOB <seg<6>> must be placed at site P42.Resolved that IOB <seg<7>> must be placed at site P37.Resolved that IOB <sl<0>> must be placed at site P27.Resolved that IOB <sl<1>> must be placed at site P29.Resolved that IOB <sl<2>> must be placed at site P30.Resolved that IOB <sl<3>> must be placed at site P24.Device utilization summary:   Number of External GCLKIOBs         1 out of 4      25%   Number of External IOBs            12 out of 140     8%      Number of LOCed External IOBs   12 out of 12    100%   Number of SLICEs                   31 out of 1200    2%   Number of GCLKs                     1 out of 4      25%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Phase 1.1Phase 1.1 (Checksum:98971b) REAL time: 0 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8.Phase 5.8 (Checksum:98dedc) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file dled.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 161 unrouted;       REAL time: 0 secs Phase 2: 141 unrouted;       REAL time: 0 secs Phase 3: 22 unrouted;       REAL time: 0 secs Phase 4: 0 unrouted;       REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+|         clk_BUFGP          |  Global  |   13   |  0.000     |  0.658      |+----------------------------+----------+--------+------------+-------------+|         count<24>          |   Local  |    9   |  0.316     |  3.660      |+----------------------------+----------+--------+------------+-------------+   The Delay Summary Report   The SCORE FOR THIS DESIGN is: 146The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        1.119   The MAXIMUM PIN DELAY IS:                               3.660   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.696   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------          83          65           5           8           0           0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 0 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage:  49 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file dled.ncd.PAR done.