set tool_name "ModelSim-Altera (Verilog)"
set corner_file_list {
	{{"Slow -2 1.1V 85 Model"} {agc_2_1100mv_85c_slow.vo agc_2_1100mv_85c_v_slow.sdo}}
	{{"Slow -2 1.1V 0 Model"} {agc_2_1100mv_0c_slow.vo agc_2_1100mv_0c_v_slow.sdo}}
	{{"Fast -M 1.1V 0 Model"} {agc_min_1100mv_0c_fast.vo agc_min_1100mv_0c_v_fast.sdo}}
}