library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.dt16_pkg.all;

entity p_s2m_onechnl is
    port(
        reset       : in    std_logic;
        fck32m      : in    std_logic; --來自背板的32M幀頭
       clk32m      : in    std_logic; --來自背板的32M時鐘			
       out2mhw_p   : in    std_logic_vector(7 downto 0);
       out2mhw_s   : out   std_logic
  		  );
end p_s2m_onechnl;  		 

architecture arch_p_s2m_onechnl of p_s2m_onechnl is

  signal en_2m : std_logic;  
  signal en_2m_lock : std_logic_vector(2 downto 0);
  signal count : std_logic_vector(4 downto 0);
  signal count1 : std_logic_vector(2 downto 0);
  signal out2m_tmp : std_logic_vector(7 downto 0);
  signal out2mhw_locked : std_logic_vector(7 downto 0);
  signal out2mhw_s_lock : std_logic_vector(7 downto 0);
  

begin

  process(fck32m,clk32m)
  begin
    if reset='1' then 
      count<=(others => '0');
    elsif clk32m'event and clk32m='1' then
      count<=count+'1';
    end if;
  end process;
  
  process(clk32m)
  begin
    if clk32m'event and clk32m='1' then
      if count(3 downto 0) = "0100" then --
        en_2m<='1';
      else
        en_2m<='0';
      end if;
    end if;
  end process;
  
  process(clk32m)
  begin
    if clk32m'event and clk32m='1' then
      en_2m_lock<=en_2m_lock(1 downto 0)& en_2m;
    end if;
  end process;
      
  process(fck32m,clk32m)
  begin
    if fck32m='1' then
       count1<="000";
    elsif clk32m'event and clk32m='1' then
      if en_2m='1' then
        count1<=count1+'1';
      end if;
    end if;
  end process;

  process(clk32m,en_2m_lock)       --reset,              
  begin                                           
    --if reset='1' then                             
    --  out2m_tmp<=(others =>'0');                  
    --els
    if clk32m'event and clk32m='1' then                         
      if en_2m_lock(2)='1' then   --en_2m
        if count1(2 downto 0)="001" then      --    000  
          out2m_tmp<=out2mhw_p;                               
        else
          out2m_tmp<=out2m_tmp(6 downto 0) & '1';   
        end if;
      end if;                                     
    end if;                                       
  end process;                                    
  
  process(clk32m,en_2m)
  begin
    if clk32m'event and clk32m='1' then
      if en_2m='1' then
        out2mhw_locked<=out2mhw_locked(6 downto 0) & out2m_tmp(7);
      end if;
    end if;
  end process;
  
  process(clk32m)
  begin
    if clk32m'event and clk32m='1' then
      out2mhw_s_lock<=out2mhw_s_lock(6 downto 0) & out2mhw_locked(2);
    end if;
  end process;
  
  out2mhw_s<= out2mhw_s_lock(1);--out2m_tmp(7);
  


end arch_p_s2m_onechnl;