--文件名：PL_CPSK2
--功能：基于VHDL硬件描述語言，對(duì)CPSK調(diào)制的信號(hào)進(jìn)行解調(diào)
--最后修改日期：2004.3.16
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PL_CPSK2 is
port(clk       :in std_logic;                --系統(tǒng)時(shí)鐘
     start     :in std_logic;                --同步信號(hào)
     x       :in std_logic;                --調(diào)制信號(hào)
     y       :out std_logic);              --基帶信號(hào)
end PL_CPSK2;
architecture behav of PL_CPSK2 is
signal q:integer range 0 to 3;       
begin
process(clk)                              --此進(jìn)程完成對(duì)CPSK調(diào)制信號(hào)的解調(diào)
begin
if clk'event and clk='1' then 
   if start='0' then q<=0;
   elsif q=0 then q<=q+1;               --在q=0時(shí)，根據(jù)輸入信號(hào)x的電平來進(jìn)行判決
      if x='1' then y<='1';     
      else y<='0';
      end if;
   elsif q=3 then q<=0;
   else  q<=q+1;
   end if;
end if;
end process;
end behav;