library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--  library UNISIM;
--  use UNISIM.VComponents.all;

entity lcd913 is
    Port ( clk: in std_logic;
           rs : out std_logic;
           rw : out std_logic;
           Enable: out std_logic;
		   s: out std_logic_vector(7 downto 0));
end lcd913;
architecture Behavioral of lcd913 is
TYPE AD_STATES IS(S0,S1,S2,S3,S4,S5,S8,S9,S10,S11,s12,s13);
SIGNAL CURRENT_STATE,NEXT_STATE:AD_STATES; 
signal newclk: std_logic; 
--subtype state_type is std_logic_vector(3 downto 0);
--signal current_state:state_type;
--signal next_state:state_type;
--constant s0:state_type:="0000";
--constant s1:state_type:="0001";
--constant s2:state_type:="0010";
--constant s3:state_type:="0011";
--constant s4:state_type:="0100";
--constant s5:state_type:="0101";
--constant s6:state_type:="0110";
--constant s7:state_type:="0111";
--constant s8:state_type:="1000";
--constant s9:state_type:="1001";
--constant s10:state_type:="1010";
--constant s11:state_type:="1011";
begin

process(clk)
	variable count: integer;
begin
	if(clk'event and clk='1' )then
				count:=count+1;
                if count=45000 then 
                current_state<=next_state;
                count:=0;
                end if;  
		end if;

end process;

process(current_state)
begin 
case current_state is
     when s0=>
		Enable<='1';
		rs<='0';
		rw<='0';
		s<="00110000";
		next_state<=s1;

     when s1=>
        rs<='0';
		rw<='0';
		s<="00110000";
		Enable<='0';
     	next_state<=s2;

	when s2=>
		Enable<='1';
		rs<='0';
		rw<='0';
		s<="00110000";
		next_state<=s3;

     when s3=>
        rs<='0';
		rw<='0';
		s<="00110000";
		Enable<='0';
     	next_state<=s4;

	when s4=>
		Enable<='1';
		rs<='0';
		rw<='0';
		s<="00001100";
		next_state<=s5;

     when s5=>
        rs<='0';
		rw<='0';
		s<="00001100";
		Enable<='0';
		next_state<=s8;

    
		
	when s8=>
		Enable<='1';
		rs<='0';
		rw<='0';
		s<="00000110";
     next_state<=s9;
	 when s9=>
        rs<='0';
		rw<='0';
		s<="00000110";
		Enable<='0';
        next_state<=s10;
     when s10=>
		Enable<='1';
		rs<='0';
		rw<='0';
		s<="00100000";
        next_state<=s11;
     when s11=>
        rs<='0';
		rw<='0';
		s<="00100000";
		Enable<='0';
        next_state<=s12;
     when s12=>
		Enable<='1';
		rs<='1';
		rw<='0';
		s<="00110001";
        next_state<=s13;
	 when s13=>
        rs<='1';
		rw<='0';
		s<="00110001";
		Enable<='0';
        next_state<=s0;
     when others=>
        next_state<=s0;
end case;
end process;		
end Behavioral;