Release 6.3i Par G.35Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.NEU-96YK9Y816SD::  Wed Apr 12 14:58:09 2006D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 send_map.ncd send.ncd
send.pcf Constraints file: send.pcfWARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 36
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:eval@xilinx.com   Thank You!Loading device database for application Par from file "send_map.ncd".   "send" is an NCD, version 2.38, device xc4vlx25, package sf363, speed -10Loading device for application Par from file '4vlx25.nph' in environment
D:/Xilinx.Device speed data version:  PREVIEW 1.46 2004-07-09.Device utilization summary:   Number of External IOBs            12 out of 240     5%      Number of LOCed External IOBs    0 out of 12      0%   Number of ILOGICs                   8 out of 448     1%   Number of OLOGICs                   2 out of 448     1%   Number of Slices                   20 out of 10752   1%   Number of BUFGs                     2 out of 32      6%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Phase 1.1Phase 1.1 (Checksum:989733) REAL time: 8 secs .Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 9 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 9 secs Phase 5.8.Phase 5.8 (Checksum:9a6fa4) REAL time: 9 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 9 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 9 secs Phase 9.27Phase 9.27 (Checksum:55d4a77) REAL time: 9 secs Writing design to file send.ncd.Total REAL time to Placer completion: 10 secs Total CPU time to Placer completion: 8 secs Phase 1: 140 unrouted;       REAL time: 10 secs Phase 2: 123 unrouted;       REAL time: 16 secs Phase 3: 22 unrouted;       REAL time: 16 secs Phase 4: 0 unrouted;       REAL time: 16 secs Total REAL time to Router completion: 16 secs Total CPU time to Router completion: 15 secs Generating "par" statistics.**************************Generating Clock Report**************************+-------------------------+----------+------+------+------------+-------------+|        Clock Net        | Resource |Locked|Fanout|Max Skew(ns)|Max Delay(ns)|+-------------------------+----------+------+------+------------+-------------+|         clk_BUFGP       |BUFGCTRL_X| No   |    6 |  0.481     |  1.913      |+-------------------------+----------+------+------+------------+-------------+|        load_BUFGP       |BUFGCTRL_X| No   |    9 |  0.582     |  2.057      |+-------------------------+----------+------+------+------------+-------------+|            clkdiv       |   Local  |      |    9 |  1.958     |  3.455      |+-------------------------+----------+------+------+------------+-------------+   The Delay Summary Report   The SCORE FOR THIS DESIGN is: 135The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        0.939   The MAXIMUM PIN DELAY IS:                               3.455   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.035   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------          95          24          20           1           0           0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 17 secs Total CPU time to PAR completion: 15 secs Peak Memory Usage:  126 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file send.ncd.PAR done.