/********************************************************************************    File Name:  txmit.v*      Version:  1.1*         Date:  January 22, 2000*        Model:  Uart Chip**      Company:  Xilinx***   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY *                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY *                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.**                Copyright (c) 2000 Xilinx, Inc.*                All rights reserved*******************************************************************************/`timescale 1 ns / 1 nsmodule txmit (din,tbre,tsre,rst,clk16x,wrn,sdo) ;output tbre ;output tsre ;output sdo ;input [7:0] din ;input rst ;input clk16x ;input wrn ;reg tbre ;reg tsre ;reg clk1x_enable ;reg [7:0] tsr ;reg [7:0] tbr ;reg parity ;reg[3:0] clkdiv ;wire clk1x ;reg sdo ;reg [3:0] no_bits_sent ;reg wrn1 ;reg wrn2 ;always @(posedge clk16x or posedge rst)beginif (rst)beginwrn1 <= 1'b1 ;wrn2 <= 1'b1 ;endelse beginwrn1 <= wrn ;wrn2 <= wrn1 ;endendalways @(posedge clk16x or posedge rst)beginif (rst)begintbre <= 1'b0 ;clk1x_enable <= 1'b0 ;endelse if (!wrn1 && wrn2) beginclk1x_enable <= 1'b1 ;tbre <= 1'b1 ;endelse if (no_bits_sent == 4'b0010)tbre <= 1'b1 ;else if (no_bits_sent == 4'b1101)beginclk1x_enable <= 1'b0 ;tbre <= 1'b0 ;endendalways @(negedge wrn or posedge rst)beginif (rst)tbr = 8'b0 ;elsebegintbr[7] = din[0] ;tbr[6] = din[1] ;tbr[5] = din[2] ;tbr[4] = din[3] ;tbr[3] = din[4] ;tbr[2] = din[5] ;tbr[1] = din[6] ;tbr[0] = din[7] ;endendalways @(posedge clk16x or posedge rst)beginif (rst)clkdiv = 4'b0 ; else if (clk1x_enable)clkdiv = clkdiv + 1 ;endassign clk1x = clkdiv[3] ;always @(negedge clk1x or posedge rst)if (rst)beginsdo <= 1'b1 ;tsre <= 1'b1 ;parity <= 1'b1 ;tsr <= 8'b0 ;endelsebeginif (no_bits_sent == 4'b0001)begintsr <= tbr ;tsre <= 1'b0 ;endelse if (no_bits_sent == 4'b0010)beginsdo <= 1'b0 ;endelseif ((no_bits_sent >= 4'b0011) && (no_bits_sent <= 4'b1010))begintsr[7:1] <= tsr[6:0] ;tsr[0] <= 1'b0 ;sdo <= tsr[7] ;parity <= parity ^ tsr[7] ;endelse if (no_bits_sent == 4'b1011)beginsdo <= parity ;endelse if (no_bits_sent == 4'b1100)beginsdo <= 1'b1 ;tsre <= 1'b1 ;endendalways @(posedge clk1x or posedge rst or negedge clk1x_enable)if (rst) no_bits_sent = 4'b0000 ;else if (!clk1x_enable)no_bits_sent = 4'b0000 ;elseno_bits_sent = no_bits_sent + 1 ;endmodule