`timescale 1 ns / 1 ns

module rcvr (data_ready,rxd,clk16x,rst,rdn,dout) ;

		input rxd ;//data input
		input clk16x ;
		input rst ;
		input rdn ;//讀鎖存信號
		output [7:0] dout ;
		output data_ready ;//數據接收完畢
		
		reg rxd1 ;
		reg rxd2 ;
		reg clk1x_enable ;
		reg[3:0]  bits_rcvd;
		reg [3:0] clkdiv ;
		reg [8:0] rsr ;//接收移位寄存器
		reg [7:0] rbr ;//數據接收緩沖器
		
		
		reg data_ready ;
		wire clk1x ;
		
  	assign dout = (!rdn) ? rbr:8'b11111111 ;//低電平處于讀狀態
	//  assign dout = 8'b00001111 ;
		
		
		always @(posedge clk16x or posedge rst)
		begin
		if (rst)
		begin
		rxd1 <= 1'b1 ;
		rxd2 <= 1'b1 ;    
		end
		else 
		begin
		rxd1 <= rxd ;  //非阻塞語句左側的值是始終沿到來前就已經存在的值，而右邊的事時鐘沿到來時新產生的值；在此，begin和end之間并不是串行的順序
		rxd2 <= rxd1 ;//寄存上一時刻的值
		end
		end
		
		always @(posedge clk16x or posedge rst)
		begin
			if (rst)
				clk1x_enable <= 1'b0;
			else if (!rxd1 && rxd2)            //下降沿開始數據的傳輸
				clk1x_enable <= 1'b1 ;
			else if (bits_rcvd == 4'b1100)          //數據超過9位的時候不再接收
				clk1x_enable <= 1'b0 ;
		end
		
		always @(posedge clk16x or posedge rst or negedge rdn)
		begin
			if (rst)
				data_ready = 1'b0 ;
			else if (!rdn)					  //接收的時候為低
				data_ready = 1'b0 ;
			else if (bits_rcvd == 4'b1011)	  //接收完畢以后data_ready置高
				data_ready = 1'b1 ;
		end
		
		always @(posedge clk16x or posedge rst)
		begin
		if (rst)
			clkdiv = 4'b0000 ;
		else if (clk1x_enable)
			clkdiv = clkdiv +1 ;
		end
		
		assign clk1x = clkdiv[3] ;//16分頻得到波特率
		
		always @(posedge clk1x or posedge rst)
		if (rst)
			begin
			rsr <= 9'b0 ;
			rbr <= 8'b0 ;
			end
		else 
		begin
			if (bits_rcvd >= 4'b0001 && bits_rcvd <= 4'b1001) 
				begin
				rsr[0] <= rxd2 ;
				rsr[8:1] <= rsr[7:0] ;
				end
			else if (bits_rcvd == 4'b1010)
		    rbr <= rsr[8:1] ;
		end
		
		always @(posedge clk1x or posedge rst or negedge clk1x_enable)
		if (rst)
			bits_rcvd = 4'b0000;
		else
			if (!clk1x_enable)
				bits_rcvd = 4'b0000 ;
			else
				bits_rcvd = bits_rcvd + 1 ;

endmodule