JDF G
// Created by Project Navigator ver 1.0
PROJECT sericommu
DESIGN sericommu
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s100
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE baud_clk.v
SOURCE control.v
SOURCE rcvr.v
SOURCE rcvr_tf.v
SOURCE receiver.v
SOURCE txmit.v
SOURCE txmit_tf.v
SOURCE uart.v
SOURCE uart_tf.v
[STRATEGY-LIST]
Normal=True